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Consumer Electronics, IEEE Transactions on

Issue 1 • Date Feb 1989

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Displaying Results 1 - 7 of 7
  • Tuner and demodulator performance for cable distributed D2-MAC TV-signals

    Publication Year: 1989 , Page(s): 1 - 10
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (520 KB)  

    Results are presented of a system study on cable distribution of D2-MAC (time-multiplexed analog component) TV signals. With bit error rate as a D2-data performance parameter and visibility of disturbing signals as a performance reference for MAC-video components, system requirements are derived and related to existing concepts. The D2-MAC TV-signal is a time multiplex consisting of a duobinary D2-data part at a 10.125 Mb/s bitrate and a MAC-video part. The -time compression factor for luminance is 3/2; for both of the chrominance components the factor is 3. AM-vestigal sideband transmission on the cable is assumed with a vestigal sideband of VSB=0.75 MHz, and Nyquist filtering in the receiver, while 10% residual carrier is applied during black signal levels and 100% carrier is applied during white. The logical `1' -levels of the duobinary D2-data are specified at 19% and 91% with respect to the carrier level during white signal levels. It was found that the out-of-channel selectivity requirements are more severe than for conventional TV standards if no video-scrambling is applied. This conclusion can be extended to all time-multiplexed video systems. The performance of existing quasisynchronous demodulator concepts is insufficient for proper data recovery. Tilt is a critical parameter if no correction techniques are applied. The measuring methods as used for D2-data to investigate its sensitivity for tolerances on transmission parameters are found to be also suitable for other practical investigations on digital transmissions View full abstract»

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  • Alignment-free digital videorecorder-servo concept

    Publication Year: 1989 , Page(s): 11 - 15
    Cited by:  Papers (2)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB)  

    An alignment-free servo concept for video recorders is presented that uses a microprocessor for digital regulation in combination with a novel drum-motor-control concept. The system is also capable of doing some of the required mechanical adjustments by itself. This servo concept is based on a general-purpose microcontroller with an enhanced-purpose microcontroller timer structure for measuring time intervals and generating output signals with a resolution of about 1 μs. In addition to the microprocessor, only a few amplifiers are needed to convert the incoming signals into logic levels and the pulse-length-modulated regulation signals into analog values. The drum motor is a DC brushless type with only one optocoupler as signal reference. It is controlled by a custom IC. The following functions are covered by this implementation: (a) the optocoupler signal is decoded for commutating of the motor, generating the speed and phase signals for the microprocessor; and (b) the output stages incorporate three push-pull stages with current limiter, a voltage-controlled loop for the output current, and a thermal shutdown stage with hysteresis View full abstract»

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  • Multi channel PWM power invertors integrated in a switching power supply circuit

    Publication Year: 1989 , Page(s): 43 - 49
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (344 KB)  

    A description is given of a PWM (pulse-width modulated) power inverter circuit integrated into a conventional switching power-supply circuit. The output current of the switching power supply is distributed to several output loads by a time-sharing scheme using a PWM switching network that uses input voltage values to determine which load is energized. This circuit configuration eliminates choke coils and pulse-width modulator circuits, which are indispensable in conventional PWM power inverter circuits. The method will increase power efficiency, the cost-performance ratio, and the compactness of resulting devices, e.g. consumer electronic products and robotic systems. To verify the proposed scheme, a three-channel inverter was constructed and its DC pulse and AC output characteristics were measured. The circuit was of the flyback type, its left side being the primary switching circuit and the right side containing the output switching circuits for positive and negative DC/pulse and AC output voltages. The maximum output power was 50 W, and the power efficiency was 60% (approximately) at the switching frequency of 50 kHz View full abstract»

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  • Transmission characteristics of a power line used for data communications at high frequencies

    Publication Year: 1989 , Page(s): 37 - 42
    Cited by:  Papers (12)  |  Patents (37)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (372 KB)  

    The transmission characteristics of an installed power line used for data communication, and of a model of this actual line, were measured over the frequency range of 10 kHz-50 MHz. It was found that impedance characteristics were not greatly influenced by the working loads at high frequencies, but changed drastically at lower frequencies. For frequencies of less than 100 MHz, the transmission loss did not increase significantly with frequency. The effect of the length of the connections and variation in load impedance were both studied. It was found that for frequencies above 100 MHz, attenuation loss in the power line is divided into losses due to attenuation constant of the line and the loss occurring at wire connections located between the various wires in the wall sockets. The latter loss is proportional to the number of connections. When the transmission loss was measured by opening and closing the wire connections, the fluctuation in the loss was found to be smaller at frequencies above 1 MHz than at lower ones. The transmission loss at the higher frequency shows only fairly slight fluctuations to variations in working load on the power line. The intensity of the noise power spectrum shows a decrease of -40 B/decade. This degradation rate in the noise spectrum is greater than the rate of increase in transmission loss. The increasing transmission loss can be sufficiently compensated by amplification at the receiving end, but it is possible to keep the amplified noise below the level of disturbance View full abstract»

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  • Quality graphics for daisy-wheel word processing

    Publication Year: 1989 , Page(s): 16 - 23
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (572 KB)  

    Word processors using daisy-wheel printers presently offer quality lettering but lack graphics capability. An approach for dot-matrix emulation is suggested that may also offer high-resolution graphics. Since graphics can best be represented by dot collections, the one hundred daisy-wheel spokes can be digitized and, through appropriate selections, are able to form unlimited graphic images. The implementation of the proposed approach requires that the spokes imprints be digital, and that subcharacter horizontal displacement of the printing mechanism be available, as well as half space platen rotation. The latter two features are usually found in most daisy-wheel printers. The proposed concept calls for the assignment of various arrangements to the wheel's spokes, which in total will completely cover a predefined dot matrix area. Such areas placed in contiguity will be able to depict full-page images. Spoke dot arrangement will be firstly single-dot covering each and all matrix elements, and secondly multidot depending on the wheel's design. Examples are provided in which a dot-matrix area of (1/120")×(1/12") is considered. Using this system, daisy-wheel wordprocessing systems will be able to offer the user typeset-quality fonts as well as graphics View full abstract»

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  • A microprocessor-based dot matrix display system for Japanese Hiragana syllables

    Publication Year: 1989 , Page(s): 32 - 36
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (244 KB)  

    A microprocessor-based 5×7 dot-matrix display system for Japanese Hiragana syllables is proposed. The dot-matrix layout for each of the 68 syllables is shown. The syllable generation or the selective dots to produce a display is accomplished using a column approach, i.e. 7 dots (comprising one column) are displaced at a time with proper multiplexing, the display of each syllable is completed in 5 steps. A complete Hiragana word typically comprises one to four syllables. A four-syllable string (i.e., four 5×7 dot-matrix displays) display system is therefore proposed. The organization of the microprocessor-based hardware for such a display system is discussed and the system flowchart is given. Each character in the string is presented as a 7-bit ASCII code to the microprocessor. A program compares the character string that is input and selects the appropriate Hiragana syllables for display from a look-up table of bit patterns stored in memory. As each Hiragana syllable requires (5×7)+35 dots (or bits), five bytes of data are used to represent one syllable, ignoring the last bit of each byte. To represent the full 68 Hiragana syllables, a total of 340 bytes of memory locations are required View full abstract»

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  • Multi-numeric display systems

    Publication Year: 1989 , Page(s): 24 - 31
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (372 KB)  

    Circuitry is described for representing a binary coded decimal (BCD) number using a 16-segment display in any one of the following forms: English, Arabic, Chinese, or Hindi. The choice of number system is user-selectable. In addition to the selector switch and the display, the system uses two PROMs (programmable read-only memories) and an encode. All the components used in the display system, including the 16-segment display, are readily available commercially. It is noted that not all of the 16 segments are used for the display of the various numerals; and some are always blank. Therefore, the power requirements of the 16-segment display device are comparable to the power requirements of display devices previously reported in the literature. In addition, two other simple systems for the display of Hindi numerics are also proposed. One of these systems uses the conventional 7-segment display device and the other uses a 10-segment display device View full abstract»

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Aims & Scope

The main focus for the IEEE Transactions on Consumer Electronics is the engineering and research aspects of the theory, design, construction, manufacture or end use of mass market electronics, systems, software and services for consumers.

 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
R. Simon Sherratt, IEEE Fellow
Professor of Consumer Electronics
School of Systems Engineering
The University of Reading
Reading, Berkshire RG6 6AY  U.K.
r.s.sherratt@reading.ac.uk; sherratt@ieee.org
Phone:+44 (0) 118 3788588