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Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on

Issue 3 • Date Aug 1995

 This issue contains several parts.Go to:  Part  

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Displaying Results 1 - 24 of 24
  • Design of solder joints for self-aligned optoelectronic assemblies

    Publication Year: 1995 , Page(s): 543 - 551
    Cited by:  Papers (22)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (688 KB)  

    Self-aligning soldering is the critical technology for precision optoelectronic assembly. The pre-assembly solder joint design can improve the final alignment accuracy. In this paper, a public domain software Surface Evolver is modified as a modeling tool for the design of solder joints for self-aligned assemblies. Furthermore, for convenient and efficient design, the results from the numerical model are nondimensionalized and regressed as a polynomial regression model, which describes the relationships between the surface tension forces and the solder joint design parameters explicitly. The regression model is established based on 1100 data points calculated for solder joints with circular pads. We apply this model tool to several design case studies, including the joint array design for self-alignment and the solder assembly of a FLC/VLSI spatial light modulator. It is demonstrated that the model developed here is a very powerful and convenient tool to aid in the design of solder joints for various applications View full abstract»

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  • A self-aligned optical subassembly for multi-mode devices

    Publication Year: 1995 , Page(s): 552 - 557
    Cited by:  Papers (11)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (488 KB)  

    A completely self-aligned optical sub-assembly is described that meets the optical alignment tolerances needed for low-loss LED and PIN photodiode OSA's. Solder reflow aligns the optical device (LED or PIN photodiode) to a silicon “header,” which is mechanically aligned to a silicon fiber stub with fiducial cavities and alignment spheres. This assembly is in turn mounted in a plastic ferrule. Devices made using this alignment scheme have demonstrated losses as low as 0.5 dB relative to a butt-coupled fiber measurement View full abstract»

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  • Metallurgical reactions at the interface of Sn/Pb solder and electroless copper-plated AlN substrate

    Publication Year: 1995 , Page(s): 537 - 542
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (504 KB)  

    Intermetallic formation between electroless-plated copper and Sn/Pb solder is investigated. An interlayer is formed between copper and solder, and segregation of Pb-rich and Sn-rich phases are observed. X-ray diffraction and EDX analysis results suggest that the major intermetallic formed in the interlayer is Cu6Sn5. For the as-plated sample, the adhesion strength of Cu to the AIN substrate after 150°C aging is affected by both the recrystallization and the creep of copper. For the soldered specimen, the presence of intermetallic compound causes cracks to propagate along the intermetallic/Cu interface and results in a decrease of the adhesion strength View full abstract»

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  • Computer-controlled pressure-dispensed multimode polymer waveguides

    Publication Year: 1995 , Page(s): 572 - 577
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (560 KB)  

    An extremely simple, low-cost technique is described for rapid fabrication of polymer optical waveguides on silicon or glass substrates. Experimental results are reported for two types of multimode optical waveguides suitable for signal distribution in hybrid OEIC's. Losses as low as 0.1 dB/cm are observed View full abstract»

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  • Moisture sensitivity and reliability of plastic thermally enhanced QFP packages

    Publication Year: 1995 , Page(s): 485 - 490
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (460 KB)  

    Standard plastic quad flat packs have difficulty meeting the thermal performance requirements of devices with high power dissipation. The development of plastic thermally enhanced quad flat packs (TEQFP), which incorporate heat slugs or heat spreaders in the leadframes, provide a cost effective solution. Because the final packages are of molded plastic, TEQFP's are susceptible to moisture-induced cracking and other plastic reliability problems. This paper discusses the impact of moisture on package cracking during the board mounting process and the overall reliability of TEQFP's. Based on our study using scanning acoustic tomography and reliability stress tests, our findings reveal that TEQFP's have comparable reliability to standard PQFP's if proper storage and drying guidelines are followed View full abstract»

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  • A wafer level testability approach based on an improved scan insertion technique

    Publication Year: 1995 , Page(s): 438 - 447
    Cited by:  Papers (7)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (932 KB)  

    Testing strategies for complex WSI systems are one of the elements that may prevent the full exploitation of novel technologies, such as multichip modules (MCM's), because of the limited reliability (and quality) of the final product. The application of an efficient test strategy to the circuits of the module is necessary to achieve high-quality, cost-effective devices. The aim of this paper is to introduce a structured approach to the design of testable wafer scale devices. Bare die testability is guaranteed through the application mainly of the partial scan methodology, to provide the most convenient solution in terms of overhead and performance, while module testability is achieved through the application of the boundary scan technique View full abstract»

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  • Test vehicle for a wafer-scale field programmable gate array

    Publication Year: 1995 , Page(s): 431 - 437
    Cited by:  Papers (5)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (588 KB)  

    A test vehicle for a wafer scale field programmable gate array (FPGA) has been designed which has the potential to significantly expand FPGA capabilities. A symmetrical RAM-programmable FPGA, look-up table-based logic block and segmented channel routing are used. In this paper, the practical problems inherent to wafer scale FPGA's are investigated: i.e., redundancy, power shorts, clock distribution, cell and bus testing, and inter-cell delay. The laser-link process is used to interconnect working cells and form a defect-free array of FPGA cells. The defect avoidance algorithm is designed to minimize the delay between working cells, an important parameter for FPGA users View full abstract»

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  • Application of CFD technology to electronic thermal management

    Publication Year: 1995 , Page(s): 511 - 520
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (844 KB)  

    Application of a computational fluid dynamics (CFD) tool to the thermal modeling of free convection cooled handheld/portable products and component level products is assessed. The results of two case studies are reviewed. The first case focuses on a sealed, system level enclosure typical of portable consumer products; while the second case looks at a component level analysis of a sealed multichip module (MCM) package possessing an internal cavity. Temperatures predicted by the simulations are compared to available experimental data as a means of assessing the software's ability to adequately solve the coupled fluid dynamics/heat transfer problem. All simulation results were within 10% of experimental results for these two cases, indicating that the software is readily capable of providing good thermal performance predictions. For typical handheld portable products housed in a sealed case, the dominate mode of heat transfer from the components/circuit board to the outer case is via gaseous conduction. Convection typically fails to develop in such designs due to the dominance of viscous forces within the air confined between the circuit board and outer case View full abstract»

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  • Defect and fault tolerant interconnection strategies for WASP devices

    Publication Year: 1995 , Page(s): 416 - 423
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (648 KB)  

    While WSI-based devices continue to be of particular interest for applications with severe performance, size, weight, power, cost, and reliability requirements, various implementation constraints in the past, including interconnect defect occurrences, have prevented their successful realization. This paper presents an investigation into defect and fault tolerant interconnect strategies for a representative WSI device, WASP (WSI Associative String Processor) View full abstract»

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  • Simultaneous switching noise: influence of plane-plane and plane-signal trace coupling

    Publication Year: 1995 , Page(s): 496 - 502
    Cited by:  Papers (8)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (580 KB)  

    The paper presents an aspect of simultaneous switching noise (SSN) for CMOS drivers in packages with power distribution planes. The analysis takes into account the interactions between power distribution planes and signal traces. Coupling between these have a significant effect on the noise and must be taken into account. A model for the interaction between the signal conductors and the current paths in the power distribution planes is presented. The presence of the signal conductors is seen to have a significant impact on the SSN. The magnitude of the noise is strongly dependent on the relative positions of the signal conductors and the power and ground plane pin connections. Power and ground planes sufficiently close to each other also have significant mutual inductive coupling. This coupling will cause noise to be observed in both distribution planes, even though switching current flows in only one plane. This effect is explained View full abstract»

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  • Popcorn phenomena in a ball grid array package

    Publication Year: 1995 , Page(s): 491 - 495
    Cited by:  Papers (4)  |  Patents (46)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (484 KB)  

    Plastic ball grid array packages can be an alternative to the fine-pitch plastic quad flat package with many I/O's, due to its advantages, such as small footprint and high density interconnect, improved module assembly yield, superior thermal and electrical performances to plastic quad flat packages, etc. In spite of these many advantages, there are several concerns which hinder the plastic ball grid array package from the widespread use. One of them is the package cracking by popcorn phenomena. For the purpose of studying the popcorn phenomena, plastic ball grid array packages with 129 I/O's were tested under the pre-conditioning test conditions. Observations using scanning acoustic tomography and optical microscopy were carried out to investigate the existence of delaminations and cracks in the package, and the cracking patterns after IR reflow. Package deformations and thermomechanical stress distributions in the package were calculated by the finite element method (FEM). Three types of substrates were tried to prove that open thermal viaholes under die pad could prevent popcorn cracking during IR reflow. From the experiments and the observations, it was concluded that package cracking, which was caused by the expansion of moisture concentrated at the die adhesive layer, could be prevented using open thermal viahole under die pad. The open thermal viaholes acted as vent holes, through which the expanded water vapor could escape without causing popcorn cracking. The die-attach process using UV tape was effective in the assembly of the packages with open thermal viaholes View full abstract»

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  • Analysis of transient behavior of vertical interconnects in stacked circuit board layers using quasi-static techniques

    Publication Year: 1995 , Page(s): 521 - 531
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (924 KB)  

    Fuzz-buttons can interconnect up to fifty circuit board substrate layers in conjunction with metallic vias. As a result, the use of three-dimensional multichip modules (MCM's) with fuzz-buttons may be able to achieve very high packaging densities. On the other hand, the vertical interconnects, surrounded by different dielectric materials and passing through many ground mesh holes, are three-dimensional nonuniform transmission lines. Therefore, the electromagnetic analysis of fuzz-button interconnects is not straightforward. In this paper, we propose a method to analyze fuzz-buttons under quasistatic assumptions. We apply the electrostatic method to find the charge distribution and the distributed capacitance of the fuzz-buttons, and a quasimagnetostatic approach to calculate the inductance. By using image theory, a free space Green's function is formulated. The effect of the via holes is taken into account by utilizing the equivalence principle. A set of integral equations is established and solved by a combination of the point-matching method and Galerkin's method. An iterative algorithm is imposed to solve the matrix equations. After the equivalent nonuniform transmission line model is established, we then apply the transmission (ABCD) matrix method, allowing the propagation parameters to be obtained easily. Finally, we employ the fast fourier transform (FFT) to convert the frequency results into the tine domain. Waveform distortion, time delay, and crosstalk values for a 60 ps risetime input signal are evaluated. The quasistatic approach is compared against the finite difference time domain (FDTD) algorithms and good agreement is observed View full abstract»

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  • A test chip design for detecting thin-film cracking in integrated circuits

    Publication Year: 1995 , Page(s): 478 - 484
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (740 KB)  

    A reliability problem associated with integrated circuit assembly in molded plastic packages involves cracking in the deposited thin film layers on the top silicon surface. During thermal cycle testing, thermomechanical stresses resulting from differences in expansion coefficient can cause large relative displacements at the silicon/mold compound interface. The resulting die surface shear stresses are heavily concentrated at the corners and edges of the silicon die. These shear stresses can result in critical stress concentrations in the brittle passivation and interlayer dielectric films. This paper will report on a test chip design involving a matrix of crossing metal traces. This test chip has been designed to be sensitive to electrical leakage problems associated with thin film cracking. Two important quantities are measured. The first is electrical failure rate, which is determined as a function of metal width and proximity to the corners and edges of the die. The second is the extent over which cracking in the thin film layers progresses into the interior of the die. When overlaid on simple linear elastic finite elements models of stress, this locus of failure tends to follow lines of constant shear stress. This allows the assignment of a nominal stress value, critical in the collapse of microscopic thin film structures View full abstract»

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  • 296 lead fine pitch (0.4 mm) thin plastic QFP package with TAB interconnect

    Publication Year: 1995 , Page(s): 463 - 470
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (696 KB)  

    The quad flat pack (QFP) package has become the surface mount technology (SMT) package of choice for microprocessors and peripheral devices and is well suited for hand held computer application. To address this market segment Intel has developed a new package with a thin (2.0 mm) body for light weight, low standoff (0.25 mm maximum) for overall lower profile, in a 32 mm×32 mm body format. Tape automated bonding (TAB) interconnect from die to the leadframe is used to overcome wirebond interconnect limitations. This package provides a more manufacturable package system by using flat handling during test operation. The package is trimmed and formed subsequent to test operation and shipped in standard JEDEC thin matrix plastic trays, ready to use for SMT operation with good lead coplanarity. Package reliability is equivalent to other plastic packages. Sample packages were supplied to selected customers to help develop the 0.4 mm pin pitch SMT process, equipment and materials. The feedback/results indicate that the current base of installed SMT equipment is capable of assembling such 0.4-mm pitch packages with very little or no modification and at acceptable quality levels View full abstract»

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  • A device life cycle analysis of the WSI associative string processor

    Publication Year: 1995 , Page(s): 406 - 415
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (964 KB)  

    The paper presents a comprehensive life cycle model and analysis of the WSI Associative String Processor (WASP). The model simulates the manufacture, acceptance, and operational life of a hypothetical WASP device using discrete event simulation techniques. Manufacturing defects are modeled with the negative binomial distribution, and operational faults are modeled using an adaptation of the MIL-HDBK-217F VHSIC reliability model. A full description is given of the simulation procedures and fault tolerant structure representations used in the model. A hypothetical WASP device manufactured in poor conditions and subjected to harsh operational conditions is shown to support nearly 8000 associative processing elements (APE) after 100000 h (11.4 yr) of continuous simulated operation. A simple post-manufacture device selection procedure is demonstrated which improves this harvest figure to over 10000 APE's. A hypothetical WASP device manufactured in good conditions and subjected to mild operational conditions is shown to support an average of over 12500 APE's after 100000 h of continuous simulated operation, without device selection. An architectural parameter sensitivity analysis for the hypothetical device shows that the areas of circuit elements at the upper levels of the fault tolerance hierarchy have greater significance than those at the leaf level for both yield and reliability. A test coverage analysis demonstrates the need for a comprehensive testing strategy for WSI devices View full abstract»

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  • Influence of process parameter variations on the signal distribution behavior of wafer scale integration devices

    Publication Year: 1995 , Page(s): 424 - 430
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (580 KB)  

    With decreasing geometries of MOS transistors in VLSI devices, the influence of fluctuations of process parameters during manufacturing will become more and more important, because process tolerances are not proportionally scaled to geometries. These fluctuations result in a performance spread of the devices produced by a certain process. For instance the clock rate of a microprocessor as a typical performance indicator, can vary in a wide range. One of the key issues of the implementation of circuits using wafer scale integration technologies is the synchronous distribution of signals, either clock, data or control over a large area of silicon. Fluctuations of process parameters can have a major influence on the performance of these devices. In the following paper, an efficient method for accurate prediction of the performance spread of integrated circuits is discussed and demonstrated by simulations. All the simulations are verified by measurements on a test-circuit with a huge number of test devices. The method is applied to different signal distribution networks of wafer scale integration devices to show the sensitivity of performance to these variations View full abstract»

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  • Compliant bumps for adhesive flip-chip assembly

    Publication Year: 1995 , Page(s): 503 - 510
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (752 KB)  

    Flip-chip-on-glass (FCOG) is susceptible to electrical opens for a variety of reasons including, but not limited to, movement in the Z-axis caused by flip-chip, adhesive CTE and water absorption of the adhesive. Flip-chip assembly to co-fired ceramic and laminate substrates suffers from these problems as well as others, such as bow or twist in the substrate and bond pad height irregularities. Success with adhesive flip-chip connections to these substrates has, to date, been limited. Commercially available adhesives have either failed to produce reliable bonds, or have suffered from long cure time or a lack of reworkability. A solution to these problems has been demonstrated by forming compliant bumps on the chip or substrate bond pads using a photo-imagable polymer coated with a thin layer of gold. Bumps 17 μm tall with diameters between 17 μm and 95 μm have been fabricated and bonded. The resulting compliant bump structure provides 30% of the bump height (5 μm) within the elastic compression range. This compliance eliminates many of the demands placed on the assembly adhesives by other electrical contacting methods (such as solid metal bumps or particles). Compliant bumps allow the use of commercially available, fast curing, easily reworkable adhesives for reliable flip-chip assembly. MCC's compliant bumps have been mechanically cycled from minimum compression (needed for electrical contact) to maximum compression (based on diminishing compression distance versus applied force) 1000 times, with minimal degradation of the polymer core or metal overcoat. Assemblies have been subjected to temperature cycling and steam pot aging with substantial improvement in reliability when compared to assemblies using solid metal bumps. Using compliant bump technology, low temperature rework has been demonstrated with compliant bumped chips on glass, laminate and MCM-C substrates. Chips or substrates with compliant bumps are re-usable, a significant advantage over conventional gold bump processes where the bump structure is permanently deformed by the bonding process View full abstract»

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  • Development of 0.45-mm thick ultra-thin small outline package

    Publication Year: 1995 , Page(s): 471 - 477
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (668 KB)  

    The authors developed an ultra-thin small outline package (UTSOP) with a package thickness of 0.45 mm. In spite of its significant reduction relative to conventional TSOP's (1.0-mm thick), the inner leads of the lead frame can be bonded to the electrodes on the chip with gold wire as with conventional plastic package. It is feasible since the lead that supports the chip (support lead) through insulating tape is placed on the top side of the chip. Establishing molding technology and overcoming problems such as warping of package or chip during assembly were key points in the development of the UTSOP. The UTSOP retains the same level of reliability as a TSOP View full abstract»

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  • Design of 0.35-mm pitch QFP lead and its assembly technology

    Publication Year: 1995 , Page(s): 456 - 462
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (572 KB)  

    The solder joint reliability of a 0.35-mm lead pitch, 42-mm wide×42-mm long×23-mm high, 396 pin, ceramic quad flat package (QFP) was studied in terms of: 1) finite element analysis simulation; and 2) temperature cycling tests between -65°C and +125°C. Using the study results, physical design of the QFP leads, in terms of thickness, standoff, and Au surface finish were optimized. If the von Mises stress of a QFP solder joint can be optimized to be no more 16.7 kilogram square millimeter, we can guarantee QFP solder joint reliability over requested design life. Also, we developed a thermocompression (T/C) soldering process for the QFP View full abstract»

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  • Multigigabit multichannel optical interconnection modules for asynchronous transfer mode switching systems

    Publication Year: 1995 , Page(s): 558 - 564
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (604 KB)  

    This paper describes 2.8-Gbit/s, 5-channel optical transmitter and receiver modules for board-to-board interconnection in asynchronous transfer mode (ATM) switching systems. These modules are constructed of optical and electrical submodules. The optical submodule mainly consists of a multimode-fiber array and an optical device array. The electrical submodule is constructed by a multichip module technique with GaAs IC's and multilayer ceramic substrates. The advantage of the submodule fabric is that the submodules are independently assembled after testing. Error-free 250-m transmission is successfully demonstrated over a wide range of temperatures (from 25°C to 60°C), without automatic power control and automatic temperature control circuits in the optical transmitter module View full abstract»

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  • Analysis of multilayer-multiconductor structures on anisotropic substrates using the finite difference method

    Publication Year: 1995 , Page(s): 532 - 536
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (408 KB)  

    In this paper, the finite difference method (FDM) is employed to study the effects of anisotropy on open, closed, or partially shielded multilayer-multiconductor structures. Effects of tilting the optical axis of the substrate with respect to the axes of the structure are investigated. The method was found to be suitable for the analysis of circuit geometries appearing in microwave integrated circuits (MIC's), printed circuit boards (PCB's) and in surface acoustic wave (SAW) applications for frequencies up to 5, and in some cases, to 10 GHz View full abstract»

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  • Processing and characterization of benzocyclobutene optical waveguides

    Publication Year: 1995 , Page(s): 565 - 571
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (668 KB)  

    Digital circuits are continuing to see an increase in clock speeds which puts significant demands on the design and packaging of electronic subsystems. One possible solution is to take advantage of the high bandwidth of optics. This has clearly taken place for long-distance telecommunications, but has yet to happen at the board- or chip-level in electronic systems. While there are many reasons for this, one serious issue concerns the materials that are required to achieve optical signal transmission in the electronic system. First and foremost, the material must exhibit low optical loss. The material must also be compatible with the standard processing techniques of printed wiring boards, multichip modules, or integrated circuits. In addition, the materials must be easily processed into the desired optical structures. In this paper, we present our work on using benzocyclobutene as an optical waveguide material. Benzocyclobutene is an advanced organic polymer that is ideally suited as a dielectric layer in high-speed digital circuits. We show that as a waveguide material, single-mode (1300 nm) optical waveguides can be fabricated with losses of 0.81 dB/cm. Detailed processing conditions are discussed View full abstract»

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  • Modeling intermediate tests for fault-tolerant multichip module systems

    Publication Year: 1995 , Page(s): 448 - 455
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (652 KB)  

    This paper presents analytical models for evaluating intermediate tests for yield enhancement and quality assurance of systems manufactured using fault-tolerant multichip modules (MCM's) for massively parallel computing (MPC). In the proposed approaches, we employ both a novel Markov model and a so-called working-test-set to compute the yield. Unlike a previous method which utilizes a binomial distribution, our scheme can employ intermediate tests to meet MCM quality requirements effectively. Several strategies for appropriately testing fault-tolerant MCM's have been proposed, but little analytical evaluation has been performed. In this paper, it is shown that an efficient test strategy with a modest level of redundancy may exist to achieve virtually 100% first-pass MCM yield for a particular system. We note that a yield-analysis model employing the LRTWS (Least Recently Tested in WS) test strategy proposed in this paper may provide a very good figure of merit due to its cost, delivery, number of tests and reliability benefits for current technology. Extensive parametric results for the analysis are provided to show that our approach can be applied to calculate the overall yield for fault-tolerant MCM's more accurately and efficiently, thereby improving upon the reliability and quality of the entire system View full abstract»

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  • Electrical packaging impact on source components in optical interconnects

    Publication Year: 1995 , Page(s): 578 - 595
    Cited by:  Papers (2)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1228 KB)  

    A simulation study of source module components for use within optical interconnect systems is described. SPICE models of laser diodes, CMOS drivers, and electrical packages are developed and exercised to evaluate overall source module performance. Performance metrics for power dissipation, signal latency, wavelength chirp, and signal fidelity are used. The effects of laser diode threshold current, bias condition, and driving current level are determined with respect to these metrics. The influence of driver type and electrical packaging technologies on source module performance is also evaluated. Transmission Line models of printed wiring board (PWB), tape automated bonding (TAB), and flip-chip bonding (C4) are used to study package related effects. It is found that under appropriate operating conditions, PWB can achieve acceptable noise, power, and latency performance for data rates up to 500 MHz while flip-chip bonding is required to exceed data rates of 800 MHz for the cases studied View full abstract»

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Aims & Scope

This Transaction ceased production in 1998. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope