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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 8 • Date Aug. 1995

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Displaying Results 1 - 13 of 13
  • Comments on "Test efficiency analysis of random self-test of sequential circuits"

    Publication Year: 1995 , Page(s): 1044 - 1045
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (198 KB)  

    For the original article see ibid., vol. 10, no. 3, p. 390-98 (1991). In the aforementioned paper by S. Sastry and A. Majumdar the testing effectiveness of random pattern techniques is studied and the authors claim to give complete analytical solutions to the problem of estimating such an effectiveness. The commenters point out that the analysis is based on an oversimplified circuit model, and, therefore, the conclusions are invalid. They comment on the analysis and explain its weakness, especially with respect to the built-in self-test (BIST) technique referred to as circular self-test path (CSTP).<> View full abstract»

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  • Datapath synthesis using a problem-space genetic algorithm

    Publication Year: 1995 , Page(s): 934 - 944
    Cited by:  Papers (24)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1012 KB)  

    This paper presents a new approach to datapath synthesis based on a problem-space genetic algorithm (PSGA). The proposed technique performs concurrent scheduling and allocation of functional units, registers, and multiplexers with the objective of finding both a schedule and an allocation which minimizes the cost function of the hardware resources and the total time of execution. The problem-space genetic algorithm based datapath synthesis system (PSGA-Synth) combines a standard genetic algorithm with a known heuristic to search the large design space in an intelligent manner. PSGA-Synth handles multicycle functional units, structural pipelining, conditional code and loops, and provides a mechanism to specify lower and upper bounds on the number of control steps. The PSGA-Synth was tested on a set of problems selected from the literature, as well as larger problems created by us, with promising results. PSGA-Synth not only finds the best known results for all the test problems examined in a relatively small amount of CPU time, but also has the ability to efficiently handle large problems View full abstract»

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  • Synthesis of hazard-free multilevel logic under multiple-input changes from binary decision diagrams

    Publication Year: 1995 , Page(s): 974 - 985
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1096 KB)  

    We describe a new method for directly synthesizing a hazard-free multilevel logic implementation from a given logic specification. The method is based on free/ordered Binary Decision Diagrams (BDD's), and is naturally applicable to multiple-output logic functions. Given an incompletely-specified (multiple-output) Boolean function, the method produces a multilevel logic network that is hazard-free for a specified set of multiple-input changes. We assume an arbitrary (unbounded) gate and wire delay model under a pure delay (PD) assumption, we permit multiple-input changes, and we consider both static and dynamic hazards under the fundamental-mode assumption. Our framework is thus general and powerful. While it is not always possible to generate hazard-free implementations using our technique, we show that in some cases hazard-free multilevel implementations can be generated when hazard-free two-level representations cannot be found. This problem is generally regarded as a difficult problem and it has important applications in the field of asynchronous design. The method has been automated and applied to a number of examples View full abstract»

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  • Asynchronous circuit synthesis with Boolean satisfiability

    Publication Year: 1995 , Page(s): 961 - 973
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1288 KB)  

    Asynchronous circuits are widely used in many real time applications such as digital communication and computer systems. The design of complex asynchronous circuits is a difficult and error-prone task. An adequate synthesis method will significantly simplify the design and reduce errors. In this paper, we present a general and efficient partitioning approach to the synthesis of asynchronous circuits from general Signal Transition Graph (STG) specifications. The method partitions a large signal transition graph into smaller and manageable subgraphs which significantly reduces the complexity of asynchronous circuit synthesis. Experimental results of our partitioning approach with large number of practical industrial asynchronous circuit benchmarks are presented. They show that, compared to the existing asynchronous circuit synthesis techniques, this partitioning approach achieves many orders of magnitude of performance improvements in terms of computing time, in addition to the reduced circuit implementation area. This lends itself well to practical asynchronous circuit synthesis from general STG specifications View full abstract»

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  • Fast signature computation for BIST linear compactors

    Publication Year: 1995 , Page(s): 1037 - 1044
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (712 KB)  

    Signature computation for linear compactors in a BIST environment is a computationally intensive process. In this paper, a fast compaction simulation algorithm is presented which uses superposition and look-up tables. While keeping memory requirements reasonable, this algorithm has a speedup advantage of at least one order of magnitude over traditional algorithms, and offers a threefold speedup over recently published “fast” algorithms. Our algorithm is also applicable to any linear compactor - while existing algorithms are restricted to only one type of compactor. Simulation results comparing the speed and memory requirements of the proposed compaction algorithm to that of existing compaction algorithms are given View full abstract»

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  • Exact two-level minimization of hazard-free logic with multiple-input changes

    Publication Year: 1995 , Page(s): 986 - 997
    Cited by:  Papers (33)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1172 KB)  

    This paper describes a new method for exact hazard-free logic-minimization of Boolean functions. Given an incompletely-specified Boolean function, the method produces a minimum-cost sum-of-products implementation which is hazard-free for a given set of multiple-input changes, if such a solution exists. The method is a constrained version of the Quine-McCluskey algorithm. It has been automated and applied to a number of examples. Results are compared with results of a comparable non-hazard-free method (espresso-exact). Overhead due to hazard elimination is shown to be negligible View full abstract»

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  • A pin permutation algorithm for improving over-the-cell channel routing

    Publication Year: 1995 , Page(s): 1030 - 1037
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (692 KB)  

    In standard cell design, some of the cell terminals and gates are permutable. Therefore, it is important for an over-the-cell channel router to take advantage of this so as to obtain better results. A greedy algorithm is presented to determine proper gate and terminal positions such that, when over-the-cell routers are used, the area above and below the channel can be utilized more effectively and the maximal channel density can be greatly reduced. Experimental results show that our proposed algorithm indeed considerably reduces the maximal channel density View full abstract»

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  • Improved force-directed scheduling in high-throughput digital signal processing

    Publication Year: 1995 , Page(s): 945 - 960
    Cited by:  Papers (21)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1476 KB)  

    This paper discusses improved force-directed scheduling and its application in the design of high-throughput DSP systems, such as real-time video VLSL circuits. We present a mathematical justification of the technique of force-directed scheduling, introduced by Paulin and Knight (1989), and we show how the algorithm can be used to find cost-effective time assignments and resource allocations, allowing trade-offs between processing units and memories. Furthermore, we present modifications that improve the effectiveness and the efficiency of the algorithm. The significance of the improvements is illustrated by an empirical performance analysis based on a number of problem instances View full abstract»

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  • Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution

    Publication Year: 1995 , Page(s): 998 - 1012
    Cited by:  Papers (72)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1404 KB)  

    Currents flowing in the power and ground (P&G) buses of CMOS digital circuits affect both circuit reliability and performance by causing excessive voltage drops. Excessive voltage drops manifest themselves as glitches on the P&G buses and cause erroneous logic signals and degradation in switching speeds. Maximum current estimates are needed at every contact point in the buses to study the severity of the voltage drop problems and to redesign the supply lines accordingly. These currents, however, depend on the specific input patterns that are applied to the circuit. Since it is prohibitively expensive to enumerate all possible input patterns, this problem has, for a long time, remained largely unsolved. In this paper, we propose a pattern-independent, linear time algorithm (iMax) that estimates at every contact point, an upper bound envelope of all possible current waveforms that result by the application of different input patterns to the circuit. The algorithm is extremely efficient and produces good results for most circuits as is demonstrated by experimental results on several benchmark circuits. The accuracy of the algorithm can be further improved by resolving the signal correlations that exist inside a circuit. We also present a novel partial input enumeration (PIE) technique to resolve signal correlations and significantly improve the upper bounds for circuits where the bounds produced by iMax are not tight. We establish with extensive experimental results that these algorithms represent a good time-accuracy trade-off and are applicable to VLSI circuits View full abstract»

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  • Functional timing analysis using ATPG

    Publication Year: 1995 , Page(s): 1025 - 1030
    Cited by:  Papers (5)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (604 KB)  

    Paths that are never exercised are referred to as false paths and timing analysis that ignores the delay contribution of these paths is referred to as functional timing analysis. Such timing analysis provides a more accurate estimate of circuit delay compared to conventional static timing analysis. We show how unmodified conventional Automatic Test Pattern Generators (ATPG) for stuck-at faults can be used for functional timing analysis without sacrificing computational efficiency in comparison with existing approaches to the same problem. This is a significant result since it enables us to use the entire body of work in ATPG for this problem and relieves us from re-inventing new solutions for this problem. The basic algorithm can be used under an arbitrary delay model. We provide delay computation results for all the ISCAS benchmark examples under the unit-delay and the mapped-delay models View full abstract»

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  • Template-based MOSFET device model

    Publication Year: 1995 , Page(s): 924 - 933
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (836 KB)  

    This paper describes a novel method of representing the three-dimensional MOSFET current table. The method utilizes a template constructed from a drain sweep curve. This template is compressed/expanded and scaled to match all other possible drain sweep curves. This modeling technique provides more than a 10x reduction in storage space requirements, relative to a true three-dimensional table, with little loss in accuracy. It will also be shown that the method can be extended to model the intrinsic charge surfaces View full abstract»

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  • Efficient approximation of the time domain response of lossy coupled transmission line trees

    Publication Year: 1995 , Page(s): 1013 - 1024
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (880 KB)  

    A new technique for rapidly estimating the transient response of lossy transmission line interconnect structures is introduced. The new approach, Reciprocal Expansion (REX), is similar to Asymptotic Waveform Evaluation (AWE) in that it approximates the interconnect by a low-order system. However, unlike AWE, REX expands the reciprocal of the transfer function as a Taylor series. REX has been extended to handle distributed elements directly, compute crosstalk between coupled trees, and account for frequency-dependent effects. Experimental results demonstrate that for critical underdamped interconnects, REX provides better accuracy than AWE View full abstract»

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  • Transport effects and characteristic modes in the modeling and simulation of submicron devices

    Publication Year: 1995 , Page(s): 917 - 923
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (624 KB)  

    This paper has two major goals: (1) to study the effect of the common practice of neglecting the convective terms (inertial approximation) in the hydrodynamic model in the simulation of n+ -n-n+ diodes and two dimensional MESFET devices; and (2) to test analytical criteria, formulated in terms of characteristic values of the Jacobian matrix, as a method of determining the impact of first derivative perturbation terms in this model, and in related energy transport models. This characteristic value analysis can be thought of as generalizing the usual analytical solution of first order linear systems of ordinary differential equations with constant coefficients. Concerning (1), we find that the inertial approximation is invalid near the diode junctions, and near the contact regions of the MESFET device. In regard to (2), we find a proper arrangement of terms, expressing the flux, such that the first derivative part of the system is hyperbolic, both for the hydrodynamic model and the energy transport model. For the hydrodynamic model, two forms of the heat conduction term are studied, including the case of a convective term. This suggests and validates the use of shock capturing algorithms for the simulation View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

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Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu