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Electron Devices, IEEE Transactions on

Issue 4 • Date Apr 1989

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Displaying Results 1 - 25 of 31
  • A recessed-gate In0.52Al0.48As/n+-In0.53 Ga 0.47As MIS-type FET

    Page(s): 646 - 650
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (484 KB)  

    Scaling of the In0.52 Al0.48As insulator thickness of In0.52 Ga0.48As/n+ In0.53 Ga0.47As MIS (Metal insulator semiconductor) type FETs (field effect transistors) is found experimentally to result in a drastic drop in performance below 200 Å. This is demonstrated to arise from an increase in the sheet resistance of the extrinsic portions of the device that accompanies insulator scaling. In order to solve this problem, a recessed-gate MISFET with a very thin (300 Å) n+-In0.53 Ga 0.47As cap layer has been fabricated. A 1.5-μm-long gate device showed a transconductance of 285 mS/mm and a current-gain cutoff frequency of 19.4 GHz. This result proves the ability of a thin n+ -In0.53 Ga0.47As cap to reduce source resistance and improve device performance. It is concluded that the fabricated recessed-gate structure is a promising candidate for high-performance-scaled MIS-type FETs based on thin, heavily doped In 0.53 Ga0.47As channels View full abstract»

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  • A high-performance directly insertable self-aligned ultra-rad-hard and enhanced isolation field-oxide technology for gigahertz silicon NMOS/CMOS VLSI

    Page(s): 651 - 658
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    The authors describe a novel field-oxide structure for rad-hard NMOS/CMOS VLSI. This is a three-layer structure consisting of a thin thermal oxide, a doped polysilicon sheet deposited on the thin oxide, and a thick CVD (chemical-vapor-deposited) oxide layer on the polysilicon. The small effective electrical thickness of the oxide combined with the ground potential of the polysilicon enhances the radiation hardness and maintains good isolation, even at radiation levels as high as 108 rads and above. For 100-A gate oxide, the subthreshold leakage of a MOSFET (MOS field effect transistor) with a field shield structure is less than 10-13 A/μm, and the off current is less than 10-12 A/μm, after a total dose of 100 Mrad. This structure is self-aligned and directly insertable into submicron NMOS/CMOS VLSI without any changes in the circuit design. The circuits made with this technology can operate at 2.5-3 GHz, even after a total dose of 50-100 Mrad View full abstract»

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  • Potential and electron distribution model for the buried-channel MOSFET

    Page(s): 670 - 689
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1276 KB)  

    The authors present a novel analytic model for the potential and electron distribution in the channel-depth direction for the buried-channel (BC) MOSFET (metal-oxide-semiconductor field-effect transistor). The purpose of the model is to aid in the fundamental physical understanding of the operational modes of the BC-MOSFET and the mechanisms affecting these modes. Using Poisson's equation, individual analytic expressions are formulated to predict the potential distribution and electron concentration profile under conditions of depletion, inversion, pinchoff, and accumulation as a function of the gate bias, substrate bias, and applied channel potential. While the potential distribution in the channel-depth direction enables the band-bending within the device to be visualized, the signal electron concentration profile leads to an easy physical interpretation of the modes of operation and the location of mobile charge relative to the channel surface: this is important for mobility and device speed considerations. In addition, the model can be used for device design View full abstract»

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  • Isotropic graphite multistage depressed collectors-a progress report

    Page(s): 817 - 824
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    A small, isotropic graphite electrode multistage depressed collector (MDC) was designed, fabricated, and evaluated in conjunction with a 500-W, CW (continuous wave), 4.8-to-9.6-GHz TWT (traveling wave tube). The carbon electrode surfaces were used to improve the TWT overall efficiency by minimizing the secondary electron emission losses in the MDC. The design and fabrication of the brazed graphite MDC assembly are described. The TWT and graphite electrode MDC bakeout and processing (outgassing) characteristics were evaluated and found to be comparable to those for TWTs equipped with copper electrode MDCs. The TWT and MDC performance was optimized for broadband CW operation at saturation. The average RF, overall, and MDC efficiencies were 14.9, 46.4, and 83.6%, respectively, across the octave operating band. A 1500-h CW test showed no gas buildup and excellent stability of the electrode surfaces View full abstract»

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  • Self-consistent simulation of harmonic gyrotron and peniotron oscillators operating in a magnetron-type cavity

    Page(s): 789 - 801
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    A self-consistent, large-signal computer simulation code is developed to study the interaction between the RF wave and a large helical-orbit. axis-encircling electron beam in a magnetron-type open cavity. The theory and the results of simulations of different modes of oscillations operating in an eight-vane cavity are given and discussed. A novel type of peniotron interaction that gives high efficiency for realistic thick beams is revealed View full abstract»

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  • A super-emissive self-heated cathode for high-power applications

    Page(s): 825 - 826
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    A superemissive cathode for high-power glow-discharge applications, such as high-current thyratrons, based on a self-heated thermionic emission mechanism is reported, and the mechanism is discussed. The results suggest that high-brightness cathode design for glow-discharge switches can be significantly improved. By tailoring the area of ion-beam heating, it should be possible to optimize operating conditions according to pulse length, current risetime, voltage falltime, peak current and electrode material. The superemission characteristics which are ≈2 orders of magnitude larger than typical thermionic emitters, suggest that there are a number of important applications View full abstract»

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  • High-performance Al0.15Ga0.85As/In0.53 Ga0.47As MSM photodetectors grown by OMCVD

    Page(s): 659 - 662
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    High-performance In0.53Ga0.47As metal-semiconductor-metal photodetectors using a thin lattice-mismatched AlxGa1-xAs surface layer to enhance the Schottky-barrier height have been fabricated and characterized with 1.3-μm laser sources. The dark leakage currents were reduced by a factor of five times with Al0.15Ga0.85As, when compared with GaAs or lattice-matched In0.52Al0.48As. The extrinsic quantum efficiency of a detector with a 1.0-μm absorption region was measured to be 40%. Photocurrent measurement under various illumination powers showed a linear responsivity of 0.4 A/W, and no low-frequency gain was observed. Impulse measurements showed an FWHM (full width at half maximum) of about 60 ps with no appreciable diffusion tails View full abstract»

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  • Analytical study of punchthrough in buried channel P-MOSFETs

    Page(s): 690 - 705
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1176 KB)  

    The punchthrough phenomenon in buried-channel (BC) P-MOSFETs (p-metal oxide-semiconductor field effect transistors) depletion-mode devices is investigated analytically using the voltage-doping transformation (VDT) technique. The resulting punchthrough current model shows a high degree of accuracy over a wide range of biases and channel lengths while still retaining the simplicity required for CAD (computer-aided-design) models. The mean error over about 300 experimental current-voltage points is as small as 3%. The mechanism of punchthrough in a BC-P-MOSFET is shown to be due to the DIBL (drain-induced barrier lowering) effect, which is further shown to be considerably enhanced by two effects. These effects, a surface inversion layer screening (SILS) and a drain-induced channel enlargement (DICE), are deduced and investigated analytically. The methods leading to a suppression of these effects are shown. Owing to its accuracy and generality, the present punchthrough analysis is expected to find applications in design and process optimization as well as in the simulation of advanced BC-P-MOSFETs View full abstract»

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  • Linear and nonlinear analyses of a wideband gyro-TWT

    Page(s): 802 - 810
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (660 KB)  

    Linear and nonlinear analyses on a gyrotron amplifier with a periodically disk-loaded cylindrical waveguide circuit are performed. The dispersion relation of the circuit allows for wideband interaction with a relativistic beam of moderate power (Vb=60 kV, Ib=5 A). Linear analysis of the interaction with the fundamental mode shows a gain of the order of 50-60 dB/m over a bandwidth larger than 22% and a linear phase versus frequency characteristic. Nonlinear analysis predicts 48-kW saturated output power at 5.3 GHz with 18% efficiency. The saturation length for a 20-dB tube is about 37 cm View full abstract»

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  • Resonant tunneling in double-barrier parabolic well structures

    Page(s): 745 - 749
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (496 KB)  

    The intrinsic time characteristics of a double-barrier parabolic well structure are studied numerically. One-dimensional structures with AlAs and AlGaAs barrier (and superlattice) material are investigated, and two models are considered: the actual microstructure (graded-superlattice) model and the parabolic-potential-well-model. Time-independent results such as quasi-energy levels and their widths are essentially the same for these two models. However, their time dependence has been found to be considerably different. Although the buildup times for these models are very close in magnitude, the onset of the exponential decay law for the resonant state in the parabolic potential well takes place in a very short time (after the electron density inside the well has reached its peak), thus allowing the time decay constant τd to be a good measure of the temporal decay View full abstract»

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  • Ga0.47In0.53As enhancement- and depletion-mode MISFETs with very high transconductance

    Page(s): 763 - 764
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    GaInAs metal-insulator-semiconductor field-effect transistors (MISFETs) have been fabricated on metalorganic vapor-phase-epitaxy (MOVPE) grown GaInAs layers. Enhancement-type MISFETs exhibit very high transconductances of 300 and 250 mS/mm for gate lengths of 1.5 and 3 μm, respectively. The effective channel mobility is 5800 cm2 V-1 s-1. The saturation velocity is 3.5×107 cm/s. High-frequency measurements performed on 3- and 1.5-μm-gate-lengthdevices result in a current gain cutoff frequency of 6 and 14 GHz, respectively View full abstract»

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  • Study of electrochemical etch-stop for high-precision thickness control of silicon membranes

    Page(s): 663 - 669
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    A method is described to control the thickness of single-crystal silicon membranes, fabricated by wet anisotropic etching. The technique of an electrochemical etch-stop on an epitaxial layer is used to yield better thickness control over the silicon membranes (±0.2 μm s.d.) and hence improve the reproducibility of piezoresistive pressure sensors. The output characteristics of such sensors are compared with previously fabricated pressure sensors not utilizing accurate control over membrane thickness. The benefits of the etch-stop approach become apparent when reductions in the pressure-sensitivity variations are considered. Without etch-stop, the sensitivity on one wafer varied by a factor of two from one sensor to the other. With etch-stop, the pressure sensitivity of devices fabricated on the same wafer can be controlled to within ±4% s.d View full abstract»

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  • Interdigital grids for dynamic astigmatism control in picture-tube guns

    Page(s): 777 - 784
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (568 KB)  

    Astigmatism control of Coty-29 picture tubes has been achieved through the incorporation of interdigital grids in the gun-focus electrode. These grids produce quadrupolar fields so that the focusing induced in the beam's vertical ray by the self-convergent yoke is compensated, thus eliminating the vertical flare previously observed for deflecting spots. The utility of cross plots for studying astigmatic gun/yoke systems and for measuring gun and yoke astigmatism values has been demonstrated. Measurements on a number of tubes are described and the results are compared with formulas derived from paraxial equations View full abstract»

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  • Trends in diffusion-length measurements in the original and dielectrically isolated-tub π-silicon as a function of processing

    Page(s): 750 - 760
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    An EBIC (electron-beam-induced current) analysis of diffusion length and, hence, lifetime as a function of processing history of dielectrically isolated (DI) tubs and the original π-silicon was performed with a two-dimensional computer simulation. The simulation accounts for a pear-shaped excitation volume for the surface recombination at two sidewalls and the top and bottom surfaces and for excess electron diffusion to a planar junction with a planar back contact. The different processing histories include those which have undergone minimal high-temperature heat treatment (prior to and after DI-tub formation), a phosphorus getter, and a denuded-zone treatment. It is found that the DI-tub formation process results in a slight improvement in the diffusion length, but that the denuded-zero treatment results in a significant (ten times the diffusion length in untreated material) improvement in both the original and DI-tub π-silicon View full abstract»

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  • One-dimensional non-quasi-static models for arbitrarily and heavily doped quasi-neutral layers in bipolar transistors

    Page(s): 727 - 737
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (752 KB)  

    A systematic method is presented for deriving non-quasi-static equivalent-circuit models for arbitrarily doped and heavily doped quasi-neutral layers in bipolar transistors. The large-and small-signal models developed improve various aspects of the one-dimensional Gummel-Poon model for transient and frequency circuit simulation. The improvements are assessed by computer simulation and by experiment. In the simulation of high-speed or high-frequency bipolar integrated circuits, the models show advantages over the conventional Gummel-Poon model. It is shown that non-quasi-static effects are significant in the emitter as well as the base layer. The method is developed for homojunction bipolar transistors but in principle applies also to heterojunction bipolar transistors View full abstract»

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  • Effect of energy band distortions on D/μ in heavily doped n-type silicon

    Page(s): 768 - 770
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    Calculations have shown that energy band distortions increase the magnitude of D/μ (diffusion/mobility ratio). In particular, taking band tails into account in a heavily doped material significantly changes the ratio. Therefore, any serious calculation of the transport coefficients in heavily doped materials must incorporate the effect of band tails View full abstract»

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  • The effect of interface and alloy quality on the DC and RF performance of Ga0.47In0.53As-Al0.48In 0.52As HEMTs

    Page(s): 641 - 645
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (432 KB)  

    Ga0.47In0.53As-Al0.48In0.52 As high-electron-mobility transistors (HEMTs) were fabricated in materials with varying degrees of alloy and interface disorder. The conductivities of the epitaxial layers are highest for material with the smallest amount of interface roughness and lowest for samples with poor-quality interfaces. The transconductances and unity current gain cutoff frequencies of the fabricated devices with 0.2-μm gates are similarly affected View full abstract»

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  • Modeling deep-level trap effects in GaAs MESFETs

    Page(s): 632 - 640
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    Modeling and numerical simulation have been performed to investigate the effects of deep-level-traps (DLTs) on the device characteristics of a GaAs MESFET (metal-semiconductor field-effect transistor). A simplified but realistic model of recombination-generation through DLTs is introduced into the current continuity equations, from which the space-charge contribution of DLTs in Poisson's equation is also determined. The effects of DLTs on the basic device performance as well as the backgating effect and hysteresis of drain current are analyzed in terms of ionization type, density, and position of the DLT in a two-dimensional numerical simulation View full abstract»

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  • Computationally generated velocity taper for efficiency enhancement in a coupled-cavity traveling-wave tube

    Page(s): 811 - 816
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    A computational routine has been created to generate velocity tapers for efficiency enhancement in coupled-cavity traveling-wave tubes (TWTs). Programmed into the NASA multidimensional large-signal coupled-cavity TWT computer code, the routine generates the gradually decreasing cavity periods required to maintain a prescribed relationship between the circuit phase velocity and the electron-bunch velocity. Computational results for several computer-generated tapers are compared to those for an existing coupled-cavity TWT with a three-step taper. Guidelines are developed for prescribing the bunch-phase profile to produce a taper for high efficiency. The resulting taper provides a calculated RF efficiency 45% higher than the step taper at center frequency and at least 37% higher over the bandwidth View full abstract»

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  • An advanced single-level polysilicon submicrometer BiCMOS technology

    Page(s): 712 - 719
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    An advanced VLSI (very large scale integration) technology providing high-performance n-p-n bipolar (fT=9 GHz) and submicrometer gate-length MOS (metal-oxide-semiconductor) transistors is described. This technology is intended for high-speed logic circuits operating at 5 V, where a high level of circuit integration and low power consumption is required. Features include vertical n-p-n transistors with walled, self-aligned polysilicon emitters and lightly doped extrinsic base (LDEB) extensions MOS transistors feature complementary-doped polysilicon gates and LDD (lightly doped drain) structures for both NMOS and PMOS. Optional buried contacts between the polysilicon layer and all junctions in the silicon substrate are provided. Polysilicon emitters, MOS gates, base/collector, and source/drain regions are silicided. In addition, a fully planarized metal interconnect scheme incorporating nonselective CVD (chemical-vapor-deposited) tungsten and vertical-walled contacts and vias is utilized View full abstract»

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  • Modeling of microwave semiconductor devices using simulated annealing optimization

    Page(s): 761 - 762
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (180 KB)  

    A combinatorial optimization method is applied to the problem of device model optimization. A heuristic optimization technique called simulated annealing is applied to optimize the model parameters so that the device can be accurately simulated by the resulting model. This method avoids entrapment in the local minima of the objective function. Another application of this optimization process is to provide useful device parameters for a device process engineer. The effectiveness of this approach has been demonstrated by results from three test cases View full abstract»

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  • Base spreading resistance of square-emitter transistors and its dependence on current crowding

    Page(s): 770 - 773
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (276 KB)  

    The internal DC and small-signal low-frequency base-spreading resistances of a square-emitter transistor have been calculated analytically as a function of base current. Simplifying assumptions result in a nonlinear differential equation with a simple explicit solution. The validity of the assumptions has been checked by exact numerical device simulation. The error of the analytical approximation has a maximum of only 11% at negligible current crowding (rBi-rBi,0=rs /32 instead of the exact value rs/28.6). In the total operating range of interest, the error of the analytical expression for rBi can be dropped to negligible values if the exact value of rBi,0 is inserted View full abstract»

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  • Application of AlGaAs/GaAs HBTs to high-speed CML logic family fabrication

    Page(s): 625 - 631
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (848 KB)  

    Discusses the design, fabrication, and performance of the first small-scale integrated logic family, including a current-mode-logic (CML)N inverter, OR/NOR, NAND/OR. exclusive OR/NOR gates, and master-slave flip-flops, implemented using self-aligned AlGaAs/GaAs heterojunction bipolar transistors (HBTs). The HBTs incorporated in the ICs (integrated circuits) are based on a 2.5-μm emitter design rule and exhibit a current gain of 40, a cutoff frequency of 50 GHz, an estimated CML gate-propagation delay time of 24.7 ps, and a non-threshold-logic gate-propagation delay time of 12.3 ps. Successful operation of the logic circuits has been predicted using a SPICE-F simulator and verified experimentally View full abstract»

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  • The effects of gate field on the leakage characteristics of heavily doped junctions

    Page(s): 720 - 726
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    A gated-diode leakage-current mechanism is reported that is dominant below 4 V in ULSI (ultra-large-scale integration) gated-diode structures. The leakage mechanism has been fully characterized for gated junctions inherent in DRAM (dynamic random access memory) storage capacitor structures and the source-drain junctions of both PMOS (p-metal-oxide-semiconductor) and NMOS device structures. The salient features of the observed leakage current are that it is thermally activated and its magnitude increases exponentially with applied gate voltage. By making measurements at cryogenic temperatures it was possible to distinguish between the reported mechanism and that of band-to-band tunneling that occurs at higher applied voltages. A theoretical model is proposed that attributes the leakage mechanism to transport-limited thermal generation within the depleted space-charge region of the heavily doped side of junctions. An analytical expression derived from the proposed model is shown to be in excellent agreement with experimental results View full abstract»

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  • An analytical model for pinchoff voltage evaluation of ion-implanted GaAs MESFETs

    Page(s): 765 - 768
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (228 KB)  

    The authors describe an analytical model for accurate evaluation of pinchoff voltage and channel thickness of ion-implanted GaAs MESFETs (metal-semiconductor field-effect transistors). A method for calculating I-V characteristics is outlined that uses pinchoff voltage and channel thickness and takes into account the effects of capping, backgating and source and drain resistances. Both single- and multiple-implantation cases are discussed View full abstract»

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IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology