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IEE Proceedings - Computers and Digital Techniques

Issue 3 • Date May 1995

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Displaying Results 1 - 9 of 9
  • Window-based surveillance strategies

    Publication Year: 1995, Page(s):233 - 236
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (224 KB)

    As distributed systems and computer networks become more sophisticated, the problem of accurately estimating the system traffic intensity increases in importance. Information about the traffic can be used, for example, by the network manager in load-dependent routing and system reconfiguration. This information can be gathered by carrying out window-based surveillance, i.e. traffic intensity is es... View full abstract»

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  • CHiRPS: a general-area parallel multilayer routing system

    Publication Year: 1995, Page(s):208 - 214
    Cited by:  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (512 KB)

    A new, highly parallel model for concurrent multilayer routing, called CHiRPS (Configurable Highly Routable Parallel System), is presented. The nucleus of CHiRPS is a very flexible pathfinder that can be easily configured, even in the presence of obstacles, to generate various commonly used pattern-based routes, such as Steiner trees with single trunk, comb trees, contour-based routes, etc., that ... View full abstract»

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  • Efficient state encoding algorithm based on hypercube construction

    Publication Year: 1995, Page(s):225 - 232
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (492 KB)

    Presents a new, efficient algorithm for the state encoding of finite-state machines which minimises the area of the combinational logic. The encoding problem is modelled as the construction of a hypercube, where the encoding of each state is given by the co-ordinate of the corresponding vertex of the D-dimensional Boolean hypercube [D=log2(number of states)]. The proposed state encoding... View full abstract»

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  • Efficient CORDIC-based systolic architectures for the discrete Hartley transform

    Publication Year: 1995, Page(s):201 - 207
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (348 KB)

    Presents two new linear systolic architectures for the 1D discrete Hartley transform (DHT). Both architectures exhibit several desired features such as regularity, modularity and high pipelineability, which make them amenable to VLSI hardware implementation. In addition, these new architectures use the CORDIC (Co-Ordinate Rotation DIgital Computer) algorithm as the basic function for each processi... View full abstract»

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  • Efficient sharing (broadcasting) of multiple secrets

    Publication Year: 1995, Page(s):237 - 240
    Cited by:  Papers (18)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (304 KB)

    Instead of using the conventional m-out-of-n perfect secret sharing scheme to protect a single secret among n users, the authors propose a secret sharing scheme based on one cryptographic assumption to protect multiple secrets. It is shown that, with this relaxation of the security requirement, secret sharing and some related secret-sharing problems, such as cheater detection and secret broadcasti... View full abstract»

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  • Design and test generation of C-testable high-speed carry-free dividers

    Publication Year: 1995, Page(s):193 - 200
    Cited by:  Papers (3)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (368 KB)

    Presents a C-testable carry-free divider circuit design and its test generation. The divider circuit takes the dividend digits, in redundant binary form, and divisor digits, in binary form, as its inputs and produces the quotient and remainder digits, also in redundant binary form. The circuit is fully testable with a test set of 72 test patterns irrespective of its bit size. To generate the test ... View full abstract»

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  • VLSI design of clustering analyser using systolic arrays

    Publication Year: 1995, Page(s):185 - 192
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (412 KB)

    Presents a VLSI architecture for clustering analysers. The proposed VLSI architecture exploits two-dimensional systolic arrays, which use a high degree of parallel and pipelined processing. The architecture dramatically reduces the immense number of processing elements which were required by previous architectures. Moreover, the same architecture can be utilised for applications with a variable nu... View full abstract»

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  • Parallel multigrid algorithms on CM-5

    Publication Year: 1995, Page(s):177 - 184
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (536 KB)

    Solutions to partial differential equations are required in many engineering applications. The multigrid method is an iterative technique for speeding up the solution of these equations. The authors describe a parallel implementation of the multigrid method on the Connection Machine CM-5 architecture. An analytic model is presented for estimating the computation and communication times of the mult... View full abstract»

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  • High-level synthesis of DSP datapaths by global optimisation of variable lifetimes

    Publication Year: 1995, Page(s):215 - 224
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (788 KB)

    COBRA (Column-Oriented Butted Regular Architecture) is a behavioural high-level synthesis tool for datapath-dominated applications. It globally optimises the synthesised datapath by performing the scheduling and allocation tasks simultaneously. COBRA uses a bit-sliced target architecture and layout style which, when compared with conventional approaches, significantly reduces the area of the final... View full abstract»

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