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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 7 • Date Jul 1995

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Displaying Results 1 - 14 of 14
  • FPAD: a fuzzy nonlinear programming approach to analog circuit design

    Publication Year: 1995 , Page(s): 785 - 793
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (800 KB)  

    FPAD, a CAD tool for the design of analog circuits, is presented. For a set of input specifications, FPAD deduces the device sizes that optimize the performance objectives while satisfying the constraint specifications. Fuzzy set theory is used to measure the degree of fulfilment of the objectives and constraints, and hence provides a measure of the design quality. Trade-offs are handled by manipulating the shape of the membership functions that reflect the fulfilment or violation of the performance specifications. FPAD allows the optimization of several objectives simultaneously since multiple objective optimization is used. The mathematical formulation of the design problem is fuzzified to support real-world terms like high, good, small, acceptable, etc. The optimization is based on analytic models to avoid a simulator in the inner optimization loop. Using this approach, a two-stage unbuffered CMOS op amp and a simple emitter follower were designed, with promising results View full abstract»

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  • Combinational and sequential logic optimization by redundancy addition and removal

    Publication Year: 1995 , Page(s): 909 - 916
    Cited by:  Papers (52)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (744 KB)  

    This paper presents a method for multilevel logic optimization for combinational and synchronous sequential circuits. The circuits are optimized through iterative addition and removal of redundancies. Adding redundant wires to a circuit may cause one or many existing irredundant wires and/or gates to become redundant. If the amount of added redundancies is less than the amount of created redundancies, the transformation of adding followed by removing redundancies will result in a smaller circuit. Based upon the Automatic Test Pattern Generation (ATPG) techniques, the proposed method can efficiently identify those wires for addition that would create more redundancies elsewhere in the network. Experiments on ISCAS-85 combinational benchmark circuits show that best results are obtained for most of them. For sequential circuits, experimental results on MCNC FSM benchmarks and ISCAS-89 sequential benchmark circuits show that a significant amount of area reduction can be achieved beyond combinational optimization and sequential redundancy removal View full abstract»

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  • On the realizability and synthesis of delay-insensitive behaviors

    Publication Year: 1995 , Page(s): 833 - 848
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1528 KB)  

    This paper presents six properties, each of which, if satisfied by all the basic circuit elements used in synthesis, will also be satisfied by any delay-insensitive (DI) behavior realized by those circuit elements. Six relevant theorems are proved. The DI behaviors of classical circuit elements (e.g., AND, OR, inverter, merge, etc.) are then examined. It is found that they all satisfy the so called unique successor set (USS) property. As a result, it is proved that any DI behavior realized by a network of classical circuit elements necessarily exhibits the USS property. Some new circuit elements are needed to realize arbitrary DI behaviors (e.g., those that do not exhibit the USS property). A set of circuit elements is proposed. It is shown that these circuit elements are sufficient to implement any determinate finite state DI system View full abstract»

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  • Massively parallel computation using a splitting-up operator method for three-dimensional device simulation

    Publication Year: 1995 , Page(s): 824 - 832
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (760 KB)  

    This paper presents a new parallel algorithm and performance results of iterative solution methods for three-dimensional MOSFET simulation with Gummel's method. A splitting-up operator method is proposed for incomplete factorization of sparse matrices arising from semiconductor device equations, suitable for parallel computations. This method is combined with the conjugate gradients and BiCGSTAB procedure to obtain a new parallel version of the iterative solution methods. Natural parallelism is realized by developing the solution method according to the natural ordering. In large-scale simulations of greater than 100000 grid nodes, the high parallel efficiency level over 90% can be achieved using a new-type massively parallel computer: ADENART with up to 256 processors. The real performance of the solution methods is superior to those calculated by the vectorized version of the ICCG and ILUBiCGSTAB methods using a vector-type supercomputer View full abstract»

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  • Determining the steady-state output of nonlinear oscillatory circuits using multiple shooting

    Publication Year: 1995 , Page(s): 882 - 889
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (656 KB)  

    In this paper, we propose a time-domain approach for computing the steady-state response of nonlinear oscillatory circuits using multiple shooting techniques. For nonautonomous circuits, the algorithm is easily adapted from the multiple shooting techniques currently used to solve boundary value problems. The nonautonomous multiple shooting algorithms must be modified to work in the autonomous case as the period T is unknown. The two algorithms developed in this paper are compared with previously proposed single shooting methods on several example circuits. Additionally, the multiple shooting algorithm is compared with single shooting on a parallel machine to demonstrate its easy adaptation to this type of computer platform. The proposed multiple shooting algorithms contain both the desirable attribute of quadratic convergence while exhibiting a larger region of convergence than previously proposed single shooting methods View full abstract»

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  • Minimum area joining of compacted cells

    Publication Year: 1995 , Page(s): 903 - 909
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (648 KB)  

    We consider the problem of joining a row of compacted cells so as to minimize the area occupied by the cells and the interconnects. The cell joining process includes cell stretching and river routing. We propose several heuristics to join a row of cells in such a way that area is minimized. The proposed heuristics are compared, experimentally with that proposed by Cheng and Despain (1989) View full abstract»

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  • Methods to improve digital MOS macromodel accuracy

    Publication Year: 1995 , Page(s): 868 - 881
    Cited by:  Papers (17)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1120 KB)  

    This paper presents accurate series-transistor reduction techniques which extend the applicability of linear and nonlinear macromodels to more complex structures through accurately modeling the channel length modulation effect, effective transconductance, input terminal position dependence, parasitic capacitances, such as gate coupling capacitances, and the body effect. Adequate solutions to address these sources of delay errors, which may total 100% or more, have not been previously provided. The significant improvement in simulation accuracy using these proposed techniques is shown. The timing macromodel used to implement these techniques is up to several hundred times faster than SPICE2 and up to several times faster than existing nonlinear macromodels. The accuracy of this macromodel over a wide range of operating conditions is demonstrated. The macromodel and reduction techniques can be used to minimize VLSI simulation time, provide fast feedback in circuit optimization, and generate accurate data for higher-level macromodels. The proposed reduction techniques apply to linear and nonlinear macromodels View full abstract»

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  • Accounting thermal noise in mathematical models of quasi-homogeneous regions in silicon devices

    Publication Year: 1995 , Page(s): 815 - 823
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (732 KB)  

    This work proposes stochastic generalizations of semiconductor fluid-dynamic and the Shockley equation systems for thermal-noise modeling in quasi-homogeneous regions of silicon devices. These stochastic systems include thermal-noise terms derived from the Langevin-equation theory. The Shockley-like stochastic model performs thermal-noise sources in drift-diffusion expressions in the form of the steady-state solution of the Langevin equation, rather than in the white-noise form. Differences from the previous drift-diffusion thermal-noise modeling and the relevant physical aspects are discussed. A quasi-stationary approximation for the Shockley-like stochastic system is considered and theoretically tested for resistor and p-n junction. The corresponding results agree with the expressions for spectral densities by H. Nyquist (1928) and M. Gupta (1982), and present a generalization in the latter case. The proposed models can be used in analytical techniques for device/circuit research/design or incorporated into CAE/CAD software and open for methods of stochastic-differential-equation theory to be applied to thermal-noise analysis within fluid-dynamic and drift-diffusion approaches View full abstract»

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  • Finite element analysis of SiGe heterojunction devices

    Publication Year: 1995 , Page(s): 803 - 814
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (940 KB)  

    Two SiGe devices, a n+-n-p heterojunction diode and an n-p-n HBT have been analyzed using a two-dimensional bipolar device simulator which is based on the finite element method. The various shape functions used in the finite element formulations have been detailed. The dependence of the device characteristics on the various Ge mole-fraction material parameters has been studied. The variation of current gain of SiGe HBT with temperature is discussed View full abstract»

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  • A preprocessor for improving channel routing hierarchical pin permutation

    Publication Year: 1995 , Page(s): 896 - 903
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (728 KB)  

    In standard cell design, many cell terminals and gates are permutable, and it is important for a channel router to take advantage of this to obtain better results. An efficient hierarchical algorithm is presented to determine the proper positions of permutable gates and cell terminals such that the results of the subsequent channel routing can be significantly improved. Experimental results show that our proposed algorithm considerably reduces the number of tracks and vias, and its time complexity is linear in the number of cell terminals View full abstract»

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  • Automatic symbolic analysis of switched-capacitor filtering networks using signal flow graphs

    Publication Year: 1995 , Page(s): 858 - 867
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (776 KB)  

    Signal flow graphs (SFG's) are a powerful technique to analyze switched-capacitor (SC) circuits in a way that provides in-depth information about their operation and direct access to the corresponding symbolic z-transfer functions. Due to lengthy and error-prone symbolic manipulations this is manually manageable for simple first- or second-order circuits, but becomes unpractical for manipulating higher-order circuits which can not be decomposed into first- and second-order ones. Hence, there is an important need to provide designers with a computer-aided tool for the SFG symbolic analysis of a broad class of SC filtering networks, as described in this paper. Rule-based techniques are employed to capture from arbitrary circuit schematic and timing diagrams the corresponding symbolic SFG leading to the automatic generation of the associated z-transfer function. Symbols can then be instantiated to numerical values to obtain measurable data on a variety of performance indicators such as total capacitor area and capacitance spread as well as the resulting nominal frequency response and its variability against component errors. This is illustrated considering a variety of examples of SC filtering networks including, besides the more traditional filters, both finite and infinite impulse response decimators View full abstract»

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  • Prim-Dijkstra tradeoffs for improved performance-driven routing tree design

    Publication Year: 1995 , Page(s): 890 - 896
    Cited by:  Papers (17)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (644 KB)  

    Analysis of Elmore delay in distributed RC tree structures shows the influence of both tree cost and tree radius on signal delay in VLSI interconnects. We give new and efficient interconnection tree constructions that smoothly combine the minimum cost and the minimum radius objectives, by combining respectively optimal algorithms due to Prim (1957) and Dijkstra (1959). Previous “shallow-light” techniques are both less direct and less effective: in practice, our methods achieve uniformly superior cost-radius tradeoffs. Timing simulations for a range of IC and MCM interconnect technologies show that our wirelength savings yield reduced signal delays when compared to shallow-light or standard minimum spanning tree and Steiner tree routing View full abstract»

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  • STYLE: a statistical design approach based on nonparametric performance macromodeling

    Publication Year: 1995 , Page(s): 794 - 802
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (808 KB)  

    Despite their potential benefits, statistical design/optimization techniques are often not routinely used by industry because of prohibitive costs and/or lack of generality. To overcome these obstacles, we present a general approach to statistical design which is computationally inexpensive and applicable to an extensive spectrum of analog-digital circuits, unlike previous inexpensive methods which limit the user to specific technologies, standard device models, and/or purely digital designs. This general applicability and cost efficiency is maintained through four factors. First, an efficient screening algorithm minimizes the dimensionality of the input parameter space by identifying the important input parameters. Second, a general, accurate, parsimonious nonparametric regression model is formulated so that a wide range of behavior between input parameters and output performances can be mapped, not just those with a linear regression relationship. Third, this approach tightly couples with a compiler-methodology based simulator which sustains the achieved flexibility through its model independence. Finally, a waveform analysis capability completely automates the procedure. An industry ECL bandgap regulator circuit illustrates the benefits of this method View full abstract»

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  • Performance-driven channel pin assignment algorithms

    Publication Year: 1995 , Page(s): 849 - 857
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (872 KB)  

    In this paper we consider two channel pin assignment problems which take circuit performance into account. The first one is the module implementation selection problem. We are given a net span bound for each critical net and each module has several possible placements of its pins. Our objective is to minimize channel density while satisfying net span constraints. We proved that this problem is NP-complete. For the case when each module has at most 2 pin placements, the problem can be transformed to the 2-SAT problem and hence is polynomial time solvable. We present a heuristic based on this algorithm to solve the general case. The second problem we consider is the module shifting problem. We are given a set of modules whose relative ordering is fixed on each side of the channel but their exact positions are not fixed. We present a polynomial time algorithm to test the feasibility of satisfying the net span constraints by shifting the modules. The algorithm is based on formulating the problem as a special integer linear programming problem which is solvable in polynomial time. We also extend our algorithms to handle multiple channels View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu