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IEEE Transactions on Computers

Issue 6 • Jun 1995

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Displaying Results 1 - 8 of 8
  • Single-reference multiple intermediate signature (SREMIS) analysis for BIST

    Publication Year: 1995, Page(s):817 - 825
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (788 KB)

    Compared to single signature analysis, checking multiple intermediate signatures has many advantages, e.g., smaller aliasing, easier computation of exact fault coverage, and shorter average test time. Conventionally, checking n signatures requires n references. Storing these references and comparing them with collected signatures imposes considerable hardware requirements. In this paper, we propos... View full abstract»

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  • A fast radix-4 division algorithm and its architecture

    Publication Year: 1995, Page(s):826 - 831
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    In this paper we present a fast radix-4 division algorithm for floating point numbers. This method is based on Svoboda's division algorithm and the radix-4 redundant number system. The algorithm involves a simple recurrence with carry-free addition and employs prescaling of the operands. In the proposed divider implementation, each radix-4 digit (belonging to set {-3,...,+3}) of the quotient and p... View full abstract»

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  • Counter-based compaction: Delay and stuck-open faults

    Publication Year: 1995, Page(s):780 - 791
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1112 KB)

    In this paper, we study the properties of all major counter-based compaction schemes when the circuit under test is affected by delay or stuck-open faults. We present an error model that accurately describes the behavior of such circuits. The error model inherits from the asymmetric error model. Using this model, we compute exact aliasing probability for any test session length; we also determine ... View full abstract»

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  • Distributed memory compiler design for sparse problems

    Publication Year: 1995, Page(s):737 - 753
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1572 KB)

    This paper addresses the issue of compiling concurrent loop nests in the presence of complicated array references and irregularly distributed arrays. Arrays accessed within loops may contain accesses that make it impossible to precisely determine the reference pattern at compile time. This paper proposes a run time support mechanism that is used effectively by a compiler to generate efficient code... View full abstract»

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  • A deterministic built-in self-test generator based on cellular automata structures

    Publication Year: 1995, Page(s):805 - 816
    Cited by:  Papers (36)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (988 KB)

    This paper proposes a new approach for designing a cost-effective, on-chip, deterministic, built-in, self-test generator. Given a set of precomputed test vectors (obtained by an ATPG tool) with a predetermined fault coverage, a simple test vector generator (TVG) is synthesized to apply the given test set in a minimal test time. To achieve this objective, cellular automata (CA) structures have been... View full abstract»

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  • Efficient mapping of ANNs on hypercube massively parallel machines

    Publication Year: 1995, Page(s):769 - 779
    Cited by:  Papers (15)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (916 KB)

    This paper presents a technique for mapping artificial neural networks (ANNs) on hypercube massively parallel machines. The paper starts by synthesizing a parallel structure, the mesh-of-appendixed-trees (MAT), for fast ANN implementation. Then, it presents a recursive procedure to embed the MAT structure into the hypercube topology. This procedure is used as the basis for an efficient mapping of ... View full abstract»

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  • INCREDYBLE: A new search strategy for design automation problems with applications to testing

    Publication Year: 1995, Page(s):792 - 804
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1192 KB)

    A new search strategy for design automation problems is proposed, that is directly applicable to circuits having a size parameter (e.g., operand size), and indirectly, to random-logic circuits as well. Under the proposed approach, exhaustive search for an optimal solution is performed for small versions of the target circuit, obtained by scaling-down all the size parameters of the circuit (e.g., b... View full abstract»

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  • Hazards, critical races, and metastability

    Publication Year: 1995, Page(s):754 - 768
    Cited by:  Papers (39)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1504 KB)

    The various modes of failure of asynchronous sequential logic circuits due to timing problems are considered. These are hazards, critical races and metastable states. It is shown that there is a mechanism common to all forms of hazards and to metastable states. A similar mechanism, with added complications, is shown to characterize critical races. Means for defeating various types of hazards and c... View full abstract»

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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org