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Solid-State Circuits, IEEE Journal of

Issue 7 • Date July 1995

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Displaying Results 1 - 19 of 19
  • Introduction to the Special Issue

    Page(s): 722 - 723
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    Freely Available from IEEE
  • A 3/5 V compatible I/O buffer

    Page(s): 823 - 825
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    The design of a digital input/output buffer is described for operation in 3.3-V IC's with 5-V input signals. The design has been processed in 0.8- and 0.6-μm CMOS processes. A comparison of results is presented View full abstract»

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  • A transistor-only switched current sigma-delta A/D converter for a CMOS speech CODEC

    Page(s): 819 - 822
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    This paper describes the design and measurement results of a 1-b A/D converter based on a transistor-only switched current (SI) second-order sigma-delta modulator. The 1-b A/D converter was simulated and processed in ES2 1.5 μm CMOS technology. The second-order filter is based on class AB switched current-integrators. The analog current memory cells in the integrator are optimized for linear operation with a strong class AB overlap region to avoid class B operation and cross-over distortion. Measurement results on the first silicon performing 11-b resolution show that this circuit technique is promising for speech CODEC A/D conversion View full abstract»

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  • A performance-driven placement tool for analog integrated circuits

    Page(s): 773 - 780
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    This paper presents a new approach toward performance-driven placement of analog integrated circuits. The freedom in placing the devices is used to control the layout-induced performance degradation within the margins imposed by the designer's specifications. This guarantees that the resulting layout will meet all specifications by construction. During each iteration of the simulated annealing algorithm, the layout-induced performance degradation is calculated from the geometrical properties of the intermediate solution. The placement tool inherently handles symmetry constraints, circuit loading effects and device mismatches. The feasibility of the approach is demonstrated with practical circuit examples View full abstract»

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  • General algorithms for a simplified addition of 2's complement numbers

    Page(s): 839 - 844
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    Two algorithms for both a simplified carry save and carry ripple addition of 2's complement numbers are presented. The algorithms form the partial products so that they exclusively have positive coefficients which eliminates the need for the common sign bit extension. This results in a reduction of circuit area by up to six full adders per row of adders when partial products are added in an N/2 or Wallace tree. Furthermore, the capacitive load of the intermediate sum and carry sign bit signals decreases by up to a factor of seven which leads to an appropriate reduction of delay. Although the algorithms are derived for multipliers they can always be applied to appropriate adder circuits View full abstract»

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  • A CMOS differential buffer amplifier with accurate gain and clipping control

    Page(s): 731 - 735
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    A CMOS fully differential buffer amplifier with accurate gain and clipping control is presented. The gain is made variable by controlling the amount of the feedback around the power amplifier by means of an additional gain control loop. A new clipping technique is used to control the clipping level of the amplifier. The amplifier is realized in a 1.2 μm CMOS process with a single 5 V power supply. Measurements confirm the presented techniques View full abstract»

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  • Symbolic pole/zero calculation using SANTAFE

    Page(s): 752 - 761
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    The aim of symbolic analysis is to gain insight into circuit behavior. To study the behavior of analog circuits, the locations of the poles and zeros have to be known. Unfortunately, no general method exists to calculate the poles and zeros symbolically for polynomials of degree greater than four from transfer functions in coefficient form. The CAD tool SANTAFE (Symbolic Analysis of Transfer Functions) applies the signal-flow graph method, which permits to keep the result in a factorized or partially factorized form. The graphic view provided by a signal-flow graph offers insight into the internal interactions between the circuit elements and, as will be demonstrated, enables the user to perform circuit knowledge-based approximations. A novel procedure based on symbolic Newton-iteration, accurately calculates high-order transfer functions in the desired pole/zero form. Another special routine, based on element weight ratios rather than numerical values, enables the simplification of large symbolic expressions without numerical values for each parameter. With the program SANTAFE, even large networks can be analyzed symbolically. This will be shown with an example of a wide band BiCMOS operational amplifier View full abstract»

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  • Design concept for radiation hardening of low power and low voltage dynamic memories

    Page(s): 826 - 829
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    A radiation hard low power, low voltage dynamic memory is obtained by the use of a dummy cell concept. Compared to conventional dummy cell concepts, this concept applies a fully sized dummy cell. By optimizing the dummy cell precharge voltage for 5 V and 3 V operation and the timing of the dummy word-line, the overall soft error rate (SER) of the chip is improved by 2 orders of magnitude. An additional improvement of 1 order of magnitude is possible for 3 V operation by adjusting substrate bias and cell plate voltage. The results are verified by an accelerated SER measurement with a radium 226 source and an additional field soft error study View full abstract»

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  • A 1.5 GHz highly linear CMOS downconversion mixer

    Page(s): 736 - 742
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    A CMOS mixer topology for use in highly integrated downconversion receivers is presented. The mixing is based on the modulation of nMOS transistors in the triode region which renders an excellent linearity independent of mismatch. With two extra capacitors added to the classical cross-coupled MOSFET-C lowpass filter structure, GHz signals can be processed while only a low-frequency opamp is required as output amplifier. The downconversion mixer has an input bandwidth of 1.5 GHz. The measured third-order intercept point (IP3) of 45.2 dBm demonstrates the high linearity. The mixer has been implemented in a 1.2 μm CMOS process. It takes up 1 mm2 of total chip area and its power consumption is 1.3 mW from a single 5 V power supply View full abstract»

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  • Design of a 100-MHz 10-mW 3-V sample-and-hold amplifier in digital bipolar technology

    Page(s): 724 - 730
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    This paper describes the design of an all-npn open-loop sample-and-hold amplifier intended for use at the front end of analog-to-digital converters. Configured as a quasidifferential topology, the circuit employs capacitive coupling between the input and output to achieve differential voltage swings of 3 V in a 3.3-V system. It also exploits the high speed of bipolar transistors to attain a sampling rate of 100 MHz with a power dissipation of 10 mW. A prototype fabricated in a 1.5-μm 12-GHz digital bipolar technology exhibits harmonics 60 dB below the fundamental with a 10-MHz sinusoidal input. The hold-mode feedthrough is less than -60 dB and the droop rate is 100 μV/ns View full abstract»

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  • A vertically integrated tool for automated design of ΣΔ modulators

    Page(s): 762 - 772
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    We present a tool that starting from high-level specifications of switched-capacitor (SC) ΣΔ modulators calculates optimum specifications for their building blocks and then optimum sizes for the block schematics. At both design levels, optimization is performed using statistical techniques to enable global design and innovative heuristics for increased computer efficiency as compared with conventional statistical optimization. The tool uses an equation-based approach at the modulator level, a simulation-based approach at the cell level, and incorporates an advanced ΣΔ behavioral simulator for monitoring and design space exploration. We include measurements taken from two silicon prototypes: (1) a 16 b @ 16 kHz output rate second-order ΣΔ modulator; and (2) a 17 b @ 40 kHz output rate fourth-order ΣΔ modulator. Both use SC fully differential circuits and were designed using the proposed tool and manufactured in a 1.2 μm CMOS double-metal double-poly technology. View full abstract»

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  • SODS: a new CMOS differential-type structure

    Page(s): 835 - 838
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    Differential-type structures to implement Boolean functions find very interesting applications in self-timed circuits. A novel structure of CMOS differential circuit called Switched Output Differential Structure (SODS) is presented in this paper. This structure has been designed modifying the LOAD circuitry of previously reported differential structures, gaining in terms of transistor-count and area. This cell has been implemented on a standard 1.5 μm technology and has served to assess the structures and compare it with previously reported differential structures. Experimental laboratory results, as well as electrical simulation, show improved timing and power performance, i.e., 470 MHz and 0.46 mW at 50 MHz, respectively, for the buffer-inverter operation, with Vdd=5 V View full abstract»

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  • A 40 Mb/s soft-output Viterbi decoder

    Page(s): 812 - 818
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    Soft-output decoding has evolved as a key technology for new error correction approaches with unprecedented performance as well as for improvement of well established transmission techniques. In this paper, we present a high-speed VLSI implementation of the soft-output Viterbi algorithm, a low complexity soft-output algorithm, for a 16-state convolutional code. The 43 mm2 standard cell chip achieves a simulated throughput of 40 Mb/s, while tested samples achieved a throughput of 50 Mb/s. The chip is roughly twice as big as a 16-state Viterbi decoder without soft outputs. It is thus shown with the design that transmission schemes using soft-output decoding can be considered practical even at very high throughput. Since such decoding systems are more complex to design than hard output systems, special emphasis is placed on the employed design methodology View full abstract»

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  • A 3.0 V 40 Mb/s hard disk drive read channel IC

    Page(s): 788 - 799
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    This paper presents a high performance low power BiCMOS mixed signal ASIC that integrates all the electronics required by a hard disk drive (HDD) read channel. The IC includes the automatic gain control (AGC) circuit, a programmable continuous-time filter, two pulse qualifiers, the servo demodulator, the time base generator, the data synchronizer, and the encoder/decoder. Constant density recording with data rates between 14 and 40 Mb/s in 1,7 Run Length Limited (RLL) format and embedded 4-burst servo are supported. All the chip's specifications are guaranteed for supply voltages ranging from 3.0-5.5 V. Programming and testing are achieved via a 3-terminal bi-directional serial interface and internal registers. Nominal power dissipation at 3.0 V supply and 40 Mb/s data rate is 360 mW. Pulse pairing and write data jitter, two key performance parameters, each measured less than 300 ps View full abstract»

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  • Calculation of the soft error rate of submicron CMOS logic circuits

    Page(s): 830 - 834
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    A method to calculate the soft error rate (SER) of CMOS logic circuits with dynamic pipeline registers is described. This method takes into account charge collection by drift and diffusion. The method is verified by comparison of calculated SER's to measurement results. Using this method, the SER of a highly pipelined multiplier is calculated as a function of supply voltage for a 0.6 μm, 0.3 μm, and 0.12 μm technology, respectively. It has been found that the SER of such highly pipelined submicron CMOS circuits may become too high so that countermeasures have to be taken. Since the SER greatly increases with decreasing supply voltage, low-power/low-voltage circuits may show more than eight times the SER for half the normal supply voltage as compared to conventional designs View full abstract»

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  • An ECL to CMOS level converter with complementary bipolar output stage

    Page(s): 781 - 787
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    A novel circuit scheme for the fast amplification of digital signals is presented. A fully complementary bipolar output stage realizes small delay and steep output signal slopes. The improved performance is achieved by intentionally saturating the bipolar output transistors, which allows one to supply the maximum current to the output. We evaluate the performance of saturated bipolar transistors fabricated on bulk silicon. Compared to known circuit schemes, the proposed circuit shows significantly reduced total delay and power dissipation. The driving capability for large capacitive loads is improved. Samples produced in a 2 μm-BiCMOS technology verify the simulated performance View full abstract»

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  • A monolithic field segment photo sensor system

    Page(s): 807 - 811
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    This contribution describes a fully integrated field segment photo sensor for use in single lens reflex cameras. It supplies measurement data from five segments and the integral value via a standard interface to the camera processor. Individual calibration data of each sensor is stored in an on-chip EEPROM. The IC has been manufactured in a standard CMOS technology. The sensor operates over more than six decades of illumination to below 1 mlux. It represents an example of complex smart sensor integration View full abstract»

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  • A CMOS rectifier-integrator for amplitude detection in hard disk servo loops

    Page(s): 743 - 751
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    In this paper a CMOS alternative amplitude detection system is presented. It is designed as an alternative for the, bipolar, amplitude detection in hard disk servo systems. The amplitude is detected by converting the input voltage to a current, rectifying the current, and integrating it on a capacitor. For this a new OTA topology and a rectifier cell are designed. This circuitry is expanded with a very linear current mirror and an automatic offset compensation system to cope with technology spread. The measured accuracy of the amplitude detector is 0.2% (9 b). This makes the circuit suitable for implementation in state-of-the art hard disk systems with very high track densities and very short access times. Because the circuit is realized in standard CMOS it is a further step toward CMOS only hard disk electronics. Because the circuit operates from a single 3 V power supply and has limited power consumption it can be used in battery powered systems View full abstract»

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  • A single-chip optical sensor with analog memory for motion detection

    Page(s): 800 - 806
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    A 64×64-pixel image sensor with full-frame analog memory and on-chip motion processor is presented. The processor consists of a charge amplifier and an analog subtractor. It uses the switched-capacitor technique and calculates the difference between the values of the signal on each pixel in successive frames. The rate can achieve up to 60 frames/s with limited area and power overhead. The analog memory required for the storage of the previous frame is implemented using implanted capacitors placed within the sensor array. Fabricated in a 1.2-μm standard CMOS process with an added metal 3 light-shielding layer, the circuit is fully functional and requires a total core area of 13 mm2 View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan