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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 3 • Date Mar 1989

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Displaying Results 1 - 12 of 12
  • Self-exercising checkers for unified built-in self-test (UBIST)

    Publication Year: 1989 , Page(s): 203 - 218
    Cited by:  Papers (33)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1560 KB)  

    An original built-in self-test (BIST) scheme is proposed aimed at covering some of the shortcomings of self-checking circuits and applicable to all tests needed for integrated circuits. In this scheme, self-checking techniques and built-in self-test techniques are combined in an original way to take advantage of each other. The result is a unified BIST scheme (UBIST), allowing high fault coverage for all tests needed for integrated circuits, e.g., offline test (design verification, manufacturing test, maintenance test) and online concurrent error detection. An important concept introduced is that of self-exercising checkers. The strongly code-disjoint property of the checkers is ensured for a very large class of fault hypotheses by internal test pattern generation, and the design of the checkers is simplified View full abstract»

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  • An approximation algorithm for the via placement problem

    Publication Year: 1989 , Page(s): 219 - 228
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (888 KB)  

    The authors consider the via placement problem that arises in multilayer printed circuit board (MPCB) layout systems. It is shown that this problem can be formulated as an integer linear max-flow problem. Since the integer linear max-flow problem is an NP-complete problem, it is unlikely that one can find an efficient algorithm for its solution. However, a solution to this via placement problem can be obtained by relaxing the integer constraints in the integer linear max-flow problem. A solution to the relaxed linear max-flow problem can be obtained by solving a linear programming problem. The procedure generates in time bounded by a low order polynomial a placement with no more than 2× dOPT density, where DOPT is the density in an optimal placement View full abstract»

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  • How to build a hardware description and measurement system on an object-oriented programming language

    Publication Year: 1989 , Page(s): 288 - 301
    Cited by:  Papers (13)  |  Patents (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1428 KB)  

    Techniques are described for applying the mechanisms of object-oriented programming languages to hardware description. Some object-oriented language mechanisms, like inheritance, directly simplify CAD (computer-aided design) programs; others, like data abstraction, allow more powerful CAD mechanisms based on them to be created. The author describes: how to extend class inheritance and to integrate it with procedural construction to simplify the description of hardware; how to create measurement methods than can measure a module whose components are described at different levels of abstraction; and how to implement a consistency-maintenance engine that ensures the consistency of the data kept for the design. The author has implemented these features in Fred, an object-oriented modeling system for VLSI modules. Fred is implemented in Flavors, an object-oriented extension of Lisp. The author also discusses how to implement its features in other languages View full abstract»

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  • O(n2) algorithms for graph planarization

    Publication Year: 1989 , Page(s): 257 - 267
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1108 KB)  

    The authors present two O(n2) planarization algorithms, PLANARIZE and MAXIMAL-PLANARIZE. These algorithms are based on A. Lempel, S. Even, and I. Cederbaum's (1967) planarity testing algorithm and its implementation using PQ-trees. Algorithm PLANARIZE is for the construction of a spanning planar subgraph of an n-vertex nonplanar graph. The algorithm proceeds by embedding one vertex at a time and, at each step, adds the maximum number of edges possible without creating nonplanarity of the resultant graph. Given a biconnected spanning planar subgraph Gp of a nonplanar graph G, the MAXIMAL-PLANARIZE algorithm constructs a maximal planar subgraph of G which contains Gp . This latter algorithm can also be used to planarize maximally a biconnected planar graph View full abstract»

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  • Automated design tool execution in the Ulysses design environment

    Publication Year: 1989 , Page(s): 279 - 287
    Cited by:  Papers (24)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (936 KB)  

    Ulysses is a VLSI computer-aided-design (CAD) environment that effectively addresses the problems associated with CAD tool integration. Specifically, Ulysses allows for the integration of a collection of individual CAD tools into a design automation (DA) system that will execute a codified design methodology. Ulysses can track the multiple partial designs that result during a complete design cycle. Furthermore, Ulysses allows the designer to interrupt the design process at any time and take control. An example involving a silicon compilation task is presented to illustrate the ability of Ulysses to execute a sequence of CAD tools automatically to generate a viable layout for an IC. This example also illustrates Ulysses' ability to recover from CAD tool failures that may result if a layout cannot be completed due to routing channel congestion or overconstrained leaf-cell boundary conditions View full abstract»

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  • A knowledge-based system for the evaluation and redesign of digital circuit networks

    Publication Year: 1989 , Page(s): 302 - 315
    Cited by:  Papers (6)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1220 KB)  

    A methodology is presented for evaluating and redesigning digital circuit networks with signal integrity problems and a tool which implements this methodology. Evaluation consists of simulating the behavior of the circuit, analyzing the simulation results to reveal signal integrity problems, and diagnosing the causes of each problem. Redesign consists of finding an appropriate method to modify the structure of a faulty circuit based on the evaluation results, forming a plan out of the operators which are included in the method and applying the plan. Evaluation and redesign of the circuit are performed in two abstraction levels. Part of the work has gone into identifying and implementing the types of circuit knowledge that are necessary for the realization of the methodology. The tool which implements the methodology is called the transmission-line troubleshooting system (TLTS). TLTS executes the evaluation-redesign loop until a problem-free circuit is obtained. TLTS is implemented in the expert-system language ORBS View full abstract»

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  • A quadrisection-based combined place and route scheme for standard cells

    Publication Year: 1989 , Page(s): 234 - 244
    Cited by:  Papers (25)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (868 KB)  

    A description is given of a placement technique based on hypergraph quadrisection. The authors have developed a standard cell placement procedure based on recursively dividing the netlist into four parts, while minimizing the division cost. They have combined two ideas for placement. One is the extension of the min-cut bisection algorithm to handle quadrisection. The second idea is the simultaneous calculation of min-cut quadrisection and hierarchical global routing. The implementation details are discussed. The results show the implementation to be competitive with simulated annealing View full abstract»

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  • On the calculation of optimal clocking parameters in synchronous circuits with level-sensitive latches

    Publication Year: 1989 , Page(s): 268 - 278
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1052 KB)  

    An algorithm has been developed for the automatic determination of the optimal clock waveforms for synchronous circuits containing level-sensitive latches. From a specification of only the number of clock phases, the rise and fall times of the clock phase transitions, and the order in which they occur, the algorithm computes the minimum time interval between the transitions, while accounting for the clock skew. Timing errors, such as incorrect hold times, are also detected. Existing procedures, in contrast, either verify if a circuit meets a given specification of these clock intervals, or they work with a very restricted set of clocking schemes. The procedure is iterative, and can be formulated as a linear programming problem. It yields an upper bound on the shortest valid clock period at each iteration. Results are presented for a simplified form of this algorithm, implemented in the transistor-level timing analysis program TAMIA View full abstract»

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  • Modeling of gate oxide shorts in MOS transistors

    Publication Year: 1989 , Page(s): 193 - 202
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (928 KB)  

    A unified approach is proposed for modeling gate oxide shorts in MOS transistors using lumped-element models. These models take into account the possible structure of gate oxide short and the resulting changes that affect the I-V characteristics of MOS transistors. They can be used with the circuit simulator to predict the performance degradation of the VLSI circuit with gate oxide shorts. Demonstrated examples of models show close agreement with the experimental data View full abstract»

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  • Quad list quad trees: a geometrical data structure with improved performance for large region queries

    Publication Year: 1989 , Page(s): 229 - 233
    Cited by:  Papers (13)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (424 KB)  

    A data structure is presented for the storage of graphical information. It is a modified multiple storage quad tree, with four lists in each leaf quad. A substantial improvement is obtained for region queries, in particular on large windows, and for tree traversal. On the other hand, only an insignificant increase of memory requirement is noticed in particular situations. The method is not complicated, so it can easily be programmed View full abstract»

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  • ESp: Placement by simulated evolution

    Publication Year: 1989 , Page(s): 245 - 256
    Cited by:  Papers (46)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1108 KB)  

    ESP (evolution-based standard cell placement) is a program package designed to perform standard cell placement including macro-block placement capabilities. It uses the novel heuristic method of simulating an evolutionary process to minimize the cell interconnection wire length. While achieving comparable results to popular simulated annealing algorithms, ESP usually requires less CPU time. A concurrent version designed to run on a network of loosely coupled processors, such as workstations connected via Ethernet, has also been developed. For medium to large circuits (>250 cells per processor) concurrent ESP achieves linear speedup View full abstract»

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  • Microprocessors functional testing techniques

    Publication Year: 1989 , Page(s): 316 - 318
    Cited by:  Papers (5)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB)  

    The authors address the functional testing of microprocessors. A method is introduced for obtaining a minimum set of instructions that replaces the whole instruction set during testing procedure. The method is illustrated on the digital signal processor TM32010 View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu