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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 1 • Date Jan 1989

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Displaying Results 1 - 10 of 10
  • Linear complexity algorithms for hierarchical routing

    Page(s): 64 - 80
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1500 KB)  

    A hierarchical procedure for net routing on l×m ×n grid-graphs, where l is the number of layers, m is the number of rows, and n is the number of columns, is presented. The hierarchy reduces the overall problem to a sequence of subproblems, where each subproblem works on an l×mn portion of the overall grid. For each subproblem, an initial constructive placement (CP) of as many nets as possible is used; then a generalized dynamic programming (DP) algorithm to solve the Steiner problem of an l×2×n grid-graph is used for any remaining nets. The CP procedure uses simplistic routing assumptions to route quickly as many nets as possible. If all nets are routed, the subproblem solution is (locally) optimal and the corresponding branch of the binary recursion tree generated by the hierarchy is pruned. For any unrouted nets, the generalized DP procedure is called to route each net, one at a time, with a run time complexity of O(K×n ) where n is the number of columns and K is a function of the grid cross section and layer/wiring restrictions. There are no a priori layer restrictions or limitations on the number of layers used; three-layer cases and even some four-layer cases are feasible for the PYRAMID 90-X View full abstract»

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  • Analysis of distributed resistance effects in MOS transistors

    Page(s): 41 - 45
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    A method of modeling the distributed source and drain resistance effects in MOS transistors is discussed. Simulations performed using this technique are validated by comparisons with purpose-built structures. The method is then used to examine a problem which arises with the use of a high-temperature interconnect in three-dimensional silicon-on-insulator technologies. The results show how the resistivity of the interconnect affects the performance of the substrate devices of this technology, and the benefits achievable through further development of the existing interconnect technologies are outlined. Finally, the procedure is used to examine the effect of reduced contact size on standard MOS devices, and results wh1ich give general guidelines to the extent of the effect are presented View full abstract»

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  • Circular self-test path: a low-cost BIST technique for VLSI circuits

    Page(s): 46 - 55
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (844 KB)  

    A technique for designing self-test VLSI circuits, referred to as circular self-test path (CSTP), is introduced. The CSTP is a feedback shift register (output of the last flip-flop is supplied to the first flip-flop) with a data communication capability. It serves simultaneously for test pattern generation and test response compaction, thereby minimizing the test schedule complexity; the whole chip is tested in a single test session. A distinguishing attribute of built-in self-test (BIST) chips designed using this technique is a low silicon area overhead, slightly exceeding that of scan path designs, but substantially lower than that of built-in logic block observer (BILBO)-based circuits. Theoretical and simulation studies were performed to demonstrate that the test pattern generation efficiency of the CTSP is comparable to that of a pseudorandom generator, regardless of the functionality of the circuit under test View full abstract»

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  • A charge-based capacitance model of short-channel MOSFETs

    Page(s): 1 - 7
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    A quasi-static two-dimensional intrinsic capacitance model for short-channel MOSFETs is discussed. It is derived based in a physically based charge-sharing scheme and implemented using a quasi-static solution of a MOS device simulator. Two-dimensional field-induced mobility degradation, velocity saturation, and short-channel effects are included in the model. The charge conservation rule holds, and channel charge partitioning is properly treated. The simulation results clearly show the importance of two-dimensional field-induced effects to short-channel MOS devices. Comparison of the simulated results with experimentally measured data shows that the model is far more reliable than the analytical one. The method can be used to link a device simulator and a circuit simulator for accurate timing calculation in both digital and analog MOS integrated circuits View full abstract»

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  • Techniques for area estimation of VLSI layouts

    Page(s): 81 - 92
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (972 KB)  

    The standard cell design style is investigated. Two probabilistic models are presented. The first model estimates the wiring space requirements in the routing channels between the cell rows. The second model estimates the number of feedthroughs that must be inserted in the cell rows to interconnect cells placed several rows apart. These models were implemented in the standard cell area estimation program PLEST (PLotting ESTimator). PLEST was used to estimate the areas of a set of 12 standard cell chips. In all cases, the estimates were accurate to within 10% of the actual areas. PLEST's estimation of a chip layout area takes only a few seconds to produce, as compared with more than 10 h to generate the chip layout itself using an industrial layout system View full abstract»

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  • Experimental evaluation of testability measures for test generation (logic circuits)

    Page(s): 93 - 97
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    The results of an extensive study of five existing testability measures when used to aid heuristics for automatic test pattern generation algorithms are presented. Each measure was evaluated using over 60000 faults in circuits of varying size and complexity. The performance of these measures was rated using several different criteria. Based on these results the performance of a composite test generation strategy that uses multiple guidance heuristics was evaluated. The results indicate that this strategy not only provides better fault coverage but also reduces the average time taken to generate a test or determine that a given fault is undetectable View full abstract»

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  • On path selection in combinational logic circuits

    Page(s): 56 - 63
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    In order to ascertain correct operation of digital logic circuits it is necessary to verify correct functional operation as well as correct operation at desired clock rates. To ascertain correct operation at desired clock rates, it is verified that signal propagation delays along a set of selected paths fall within allowed limits by applying appropriate stimuli. It has previously been suggested that an appropriate set of paths to test would be the one that includes at least one path, with maximum modeled delay, for each circuit lead or gate input. Here, algorithms to select such sets of paths with minimum cardinality are given View full abstract»

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  • Electrical-logic simulation and its applications

    Page(s): 8 - 22
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    Electrical-logic (ELogic) is a form of circuit modeling and simulation that solves for the amount of time required for a network variable to make a particular change, rather than solving for the network variables at the given time point as in conventional circuit simulation. Three ELogic algorithms are presented. The algorithms are based on the nodal analysis method and provide a continuous speed-precision tradeoff between the circuit level and logic/switch level, as well as providing more accurate timing information than existing strength-oriented logic simulation or switch-level simulation at comparable speed. These ELogic algorithms have been used to implement both a simulator, ELOSIM, and a timing verifier, E-Crystal, and experimental results from these programs are also included View full abstract»

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  • A general-purpose two-dimensional process simulator-OPUS for arbitrary structures

    Page(s): 23 - 32
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    A general-purpose two-dimensional process simulator OPUS (Oki Process simulator for ULSI Structures) for arbitrary structures is discussed. By separating a preprocessor from a main processor, OPUS can simulate any kind of impurity or material with up to eight impurities and ten materials. OPUS utilizes a finite-difference method for diffusion analysis without any coordinate transformation. In order to minimize errors due to discretization around the curved boundaries, OPUS has introduced two kinds of boundaries. The first is true boundaries by strings. The other is quasi-boundaries formed through simplifying but retaining the shape of true boundaries as long as possible. The quasi-boundaries and resulting dummy cells are used for discretization of the diffusion equation. General features of OPUS are first introduced with special emphasis on dummy cells. Errors caused by dummy cells are discussed. The capacity of OPUS is then demonstrated through application to a trench process and to a full MOS process with a sidewall View full abstract»

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  • Sizing an inverter with a precise delay: generation of complementary signals with minimal skew and pulsewidth distortion in CMOS

    Page(s): 33 - 40
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (660 KB)  

    A general procedure to size an inverter which drives a given capacitance load and which has precise pull-up and pull-down delays is discussed. This procedure is an iterative combination of a Newton-Raphson numerical method used to size the transistors, and ADVICE simulations to extract parameters used in the delay model for the inverter. The numerical method makes it possible to satisfy the delay constraints precisely, while ADVICE simulations ensure accuracy. This device-sizing procedure is then used to determine the sizes of inverters in two paths, one consisting of two inverters and the other three, each driving an arbitrary capacitive load, such that the complementary output of the two paths has minimal skew and pulsewidth distortion irrespective of the processing variations. A fully automatic procedure to achieve this requires only four ADVICE simulations and takes about four minutes of CPU time on an AMDAHL-5870 computer. The circuit designed by this procedure also has a very small skew and pulsewidth distortion with temperature variation with VDD variation, and with the input rise and fall-time variations View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

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Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu