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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 6 • Date Jun 1995

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Displaying Results 1 - 13 of 13
  • Performance driven spacing algorithms using attractive and repulsive constraints for submicron LSI's

    Publication Year: 1995, Page(s):707 - 719
    Cited by:  Papers (13)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1140 KB)

    This paper proposes one-dimensional spacing algorithms that minimize [maximize] the degree of separation [proximity] among the specified elements of a given integrated circuit layout. Number of problems on chip and MCM systems such as poor performance, higher crosstalk, lower yield etc. are related to the degree of separation [proximity]. The proposed algorithms utilize the attractive [repulsive] ... View full abstract»

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  • Energy models for delay testing

    Publication Year: 1995, Page(s):728 - 739
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1168 KB)

    We present a new formulation of the delay testing problem as an energy minimization problem. Two important applications have motivated this work. First, it can be used to efficiently generate robust and nonrobust tests for path delay faults in scan and hold type of sequential circuits. Second, It allows the design of a special class of delay fault testable circuits, called (k,K)-circuits, that hav... View full abstract»

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  • SpecCharts: a VHDL front-end for embedded systems

    Publication Year: 1995, Page(s):694 - 706
    Cited by:  Papers (17)  |  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1292 KB)

    VHDL and other hardware description languages are commonly used as specification languages during system design. However, the underlying model of those languages does not directly support the specification of embedded systems, making the task of specifying such systems tedious and error-prone. We introduce a new conceptual model, called Program-State Machines (PSM), that caters to embedded systems... View full abstract»

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  • Synthesis of application specific instruction sets

    Publication Year: 1995, Page(s):663 - 675
    Cited by:  Papers (31)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1276 KB)

    In instruction set serves as the interface between hardware and software in a computer system. In an application specific environment, the system performance can be improved by designing an instruction set that matches the characteristics of hardware and the application. We present a systematic approach to generate application-specific instruction sets so that software applications can be efficien... View full abstract»

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  • Folding a stack of equal width components

    Publication Year: 1995, Page(s):775 - 780
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    We consider two versions of the problem of folding a stack of equal width components. In both versions, when a stack is folded, a routing penalty is incurred at the fold. In one version, the height of the folded layout is given and we are to minimize width. In the other, the width of the folded layout is given and its height is to be minimized. We develop a normalization technique that permits the... View full abstract»

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  • Levelized incomplete LU factorization and its application to large-scale circuit simulation

    Publication Year: 1995, Page(s):720 - 727
    Cited by:  Papers (7)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (756 KB)

    In the simulation of large circuits, the CPU time for solving the resulting linear equations may exceed the time required for evaluating the circuit elements. The circuit size above which this occurs depends on the applied transistor model and is roughly 104 devices for a vectorizing table model. To further speed up large-scale circuit simulation, one therefore has to focus on the solut... View full abstract»

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  • Cellular automata for efficient parallel logic and fault simulation

    Publication Year: 1995, Page(s):740 - 749
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (940 KB)

    We present a unilateral 2D cellular automata (CA) model and pipelining technique to parallelize logic and fault simulation. We show that given an acyclic digraph describing the Boolean function of a combinational circuit at the gate level, whose nodes are the logic gates of the circuit and whose directed edges stand for the propagating directions of signals, we can map this digraph onto a 2D CA to... View full abstract»

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  • SIERA: a unified framework for rapid-prototyping of system-level hardware and software

    Publication Year: 1995, Page(s):676 - 693
    Cited by:  Papers (11)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1876 KB)

    Modern electronic systems contain a mix of software running on general-purpose programmable processors, algorithms hardwired into dedicated hardware such as custom boards and chips, electromechanical components, and mechanical interconnect and packaging. Far more time Is spent in designing the boards, writing the software to drive, and integrate the hardware, and other such system level issues, th... View full abstract»

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  • Non-tree routing [VLSI layout]

    Publication Year: 1995, Page(s):780 - 784
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    An implicit premise of existing routing methods is that the routing topology must correspond to a tree (i.e., it does not contain cycles). In this paper we investigate the consequences of abandoning this basic axiom, and instead we allow routing topologies that correspond to arbitrary graphs (i.e., where cycles are allowed). We show that non-tree routing can significantly improve signal propagatio... View full abstract»

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  • Reconfiguration techniques for a single scan chain

    Publication Year: 1995, Page(s):750 - 765
    Cited by:  Papers (12)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1676 KB)

    A major drawback in using scan techniques is the long test application times incurred in shifting test data in and out of a device. This problem assumes even greater significance with the rapid growth in both the number of test patterns and scan registers occurring in complex VLSI designs. This paper presents a novel methodology based on reconfiguring a single scan chain to minimize the shifting t... View full abstract»

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  • Device and circuit simulation of quantum electronic devices

    Publication Year: 1995, Page(s):653 - 662
    Cited by:  Papers (29)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (884 KB)

    Quantum electronic devices such as resonant tunneling diodes and transistors are now beginning to be used in ultrafast and compact circuit designs. These devices exhibit negative differential resistance (NDR) and/or negative transconductance in their I-V characteristics and have active dimensions of a few nanometers. Since the conventional drift-diffusion approximation is not valid for simulation ... View full abstract»

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  • On over-the-cell channel routing with cell orientations consideration

    Publication Year: 1995, Page(s):766 - 772
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (660 KB)

    Existing over-the-cell channel routers assume that the orientations of the cells are fixed. In practice, it is quite common that each cell can be horizontally flipped. This pin rearrangement flexibility should be used by over-the-cell routers to further reduce channel routing area. Given a placement of cells in multiple rows with pin terminals at the top and bottom edges of the cells and each cell... View full abstract»

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  • Delay-testable implementations of symmetric functions

    Publication Year: 1995, Page(s):772 - 775
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    We show that most symmetric functions do not have delay-testable two-level implementations. A method of transforming any untestable minimal two-level implementation of a symmetric function into a delay-testable three- or four-level one using the distributive law is presented View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu