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Electron Devices, IEEE Transactions on

Issue 6 • Date June 1995

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Displaying Results 1 - 25 of 29
  • Comment on modeling of minority-carrier transport in nonuniformly doped silicon regions with asymptotic expansions [with reply]

    Publication Year: 1995 , Page(s): 1200 - 1202
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB)  

    The most important result of a recent paper by Rinaldi [see ibid., vol. 40, p. 2307-17, 1993] was the development of a new, more accurate solution for the saturation current corresponding to a nonuniformly doped semiconductor region. Such a claim of novelty is unacceptable, since the same solution had been published earlier. This comment criticizes the liberal use of the word new in the original paper, as well as the methodology followed to derive the solutions. The Appendix suggests, however, a valuable mathematical transformation that permits a factor seven reduction of the computation time of the saturation current. A reply to the comments is appended.<> View full abstract»

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  • Correlation between forward voltage drop and local carrier lifetime for a large area segmented thyristor

    Publication Year: 1995 , Page(s): 1174 - 1179
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (824 KB)  

    The forward voltage drop for individual segments of a large area thyristor has been correlated to the local, bulk carrier lifetime by lifetime mapping of the the wafer after final device processing. The lifetime mapping was performed under high injection conditions using an all-optical technique where carriers were generated by a short YAG laser pulse and the subsequent carrier decay was monitored by an IR laser beam using free carrier absorption. The lateral resolution was ~100 μm. The lifetime map revealed heavily contaminated areas where the lifetime was reduced by more than an order of magnitude. The forward voltage drop for corresponding thyristor segments was high and, for some areas, no stable turn-on could be achieved. Deep Level Transient Spectroscopy characterization of contaminated areas confirmed the lifetime measurement results and suggest that the contamination is most likely due to metal impurities introduced in the first extended-time/high-temperature drive-in of the p-base. Device simulations showed qualitative agreement between the bulk carrier lifetime and the corresponding voltage drop View full abstract»

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  • A simple method to estimate lifetime of NMOSFET's in the circuits using DC stress data

    Publication Year: 1995 , Page(s): 1193 - 1195
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB)  

    It was experimentally found that a 10% frequency degradation of a CMOS ring oscillator operated at Vdd=6.8 volts took approximately 400 times longer than a 10% degradation of the current drive under the conventional peak substrate DC stress of an identically drawn NMOSFET at Vds=6.8 volts. In order to correlate degradation rate of the DC and AC stress, a simple analytical expression to estimate lifetime of NMOSFET's in the circuits has been developed based upon the results of accelerated DC stress on NMOSFET's and quasi-static DC stress on CMOS inverters using a HP4145A DC parametric tester. The ring oscillator lifetime is in good agreement with the estimate using this method View full abstract»

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  • Modeling the extended Schottky cathode by a boundary element method

    Publication Year: 1995 , Page(s): 1180 - 1186
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (500 KB)  

    A boundary element method has been used to analyze electron emission from an extended Schottky cathode, consisting of an infinitely long array of parallel heated wires. Space charge was ignored. It was found that the current density may be expressed by a Richardson-Duschman equation in which the argument of the exponential term is corrected by an additive factor, Q, which is a function of temperature, wire radius, wire separation, and voltage. Over the range of temperatures, wire radii, and voltages examined, Q is a nearly linear function of the square root of the applied voltage. Tentative agreement with experiment was found View full abstract»

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  • Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method. II. Quantitative evaluation

    Publication Year: 1995 , Page(s): 1149 - 1155
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (456 KB)  

    For pt. I see ibid., vol. 42, no. 6, p. 1141-48 (1995).The positive-feedback regenerative process in a p-n-p-n structure during CMOS latchup transition has been modeled by a time-varying positive transient pole. The maximum peak value of the positive pole and the time required to first initiate the positive pole are adopted as two useful and meaningful parameters to quantitatively investigate the influence of device parameters on the positive-feedback regeneration of CMOS latchup. Some design guidelines can be obtained to improve latchup immunity of CMOS IC's, View full abstract»

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  • The cryogenic operation of partially depleted silicon-on-insulator inverters

    Publication Year: 1995 , Page(s): 1100 - 1105
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (416 KB)  

    This paper describes the cryogenic operation of inverters fabricated in a partially depleted (PD) 1 μm Silicon-on-Insulator (SOI) CMOS technology. As is shown, the floating-body effects like the kink effect degrade the static transfer characteristics considerably. Generally, the effects aggravate upon cooling. Additionally, at deep cryogenic temperatures, e.g., 4.2 K, typical low-temperature anomalies, which are related to the device freeze-out, cause hysteresis effects. Ways for improvement are discussed and compared: As is shown, the PD SOT inverter anomalies can be largely reduced by using the so-called twin-gate configuration View full abstract»

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  • Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method. I. theoretical derivation

    Publication Year: 1995 , Page(s): 1141 - 1148
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (708 KB)  

    A novel method to characterize the mechanism of positive-feedback regeneration in a p-n-p-n structure during CMOS latchup transition is developed. It is based on the derived time-varying transient poles in large-signal base-emitter voltages of the lumped equivalent circuit of a p-n-p-n structure. Through calculating the time-varying transient poles during CMOS latchup transition, if is found that there exists a transient pole to change from negative to positive and then this pole changes to negative again. A p-n-p-n structure, which has a stronger positive-feedback regeneration during turn-on transition, will lead to a larger positive transient pole. The time when the positive transient pole occurs during CMOS latchup transition is the time when the positive-feedback regeneration starts. By this positive transient pole, the positive-feedback regenerative process of CMOS latchup can be quantitatively characterized View full abstract»

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  • DC and large-signal time-dependent electron transport in heterostructure devices: an investigation of the heterostructure barrier varactor

    Publication Year: 1995 , Page(s): 1070 - 1080
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (976 KB)  

    The DC and large-signal time-dependent electron transport properties of Heterostructure Barrier Varactors (HBV) are investigated using a physical model which combines drift-diffusion current transport through the heterostructure bulk with thermionic and thermionic-field emission currents imposed at the abrupt heterointerfaces in a fully self-consistent manner. A fast and accurate hydrodynamic device simulator for generic unipolar InGaAs-InAlAs on InP, InGaAs-InP on InP, and GaAs-InGaAs-AlGaAs on GaAs has been developed based on this model. The experimentally observed current-voltage and capacitance-voltage characteristics of GaAs-AlGaAs and GaAs-InGaAs-AlGaAs are compared with the simulated results over a wide range of DC bias. Large-signal time-dependent simulations at a pump frequency of 100 GHz confirm the odd-harmonic operation of these devices and indicate that multiple barrier should provide efficient frequency multiplication, especially in high order frequency multipliers, broadband frequency triplers, and quasi-optical tripler arrays View full abstract»

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  • Modeling and optimization of shallow and opaque heavily doped emitters for bipolar devices

    Publication Year: 1995 , Page(s): 1126 - 1133
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (688 KB)  

    Different analytical formulations for the minority-carrier current injected into arbitrarily doped semiconductor regions are proposed, covering the case of shallow as well as opaque emitters. Firstly, based on an original transformation of the transport equations, a different derivation and formulation of the Selvakumar and Roulston model is presented. The interesting feature of this formulation is that the expression of the injected current is formally identical to that relative to the constant doping case, thereby facilitating physical insight. All effects related to the doping dependence of transport parameters are embedded into two new physical parameters, namely a characteristic surface recombination velocity and an effective diffusion length. From the study of the dependence of these quantities upon the surface doping, it is possible to obtain a simple expression for the current injected in shallow regions, which is shown to be a useful tool in interpreting the dependence of the minority-carrier current upon all significant technological parameters, and to facilitate the optimization process. The injection in opaque regions is then discussed in detail, and the asymptotic behavior for large region widths is described. A new analytical model is presented, which, unlike all previous approaches, provides an accurate description of both the nonopaque and opaque regimes View full abstract»

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  • Modeling of CrSi2-Si and MoSi2-Si Schottky barrier contacts

    Publication Year: 1995 , Page(s): 1187 - 1189
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (224 KB)  

    Forward and reverse l-V characteristics measured on CrSi2 -Si and MoSi2Si Schottky structures were compared with simulated ones. While the CrSi2-Si shows the typical non-ideal I-V characteristics of a reverse biased Schottky contact, the MoSi2-Si exhibit the nearly ideal forward and reverse I-V characteristics. The model for numerical simulation involves the clearly defined boundary conditions which combines the thermionic-emission/diffusion theory with the generation recombination theory and has the closed form View full abstract»

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  • Effects of gate recess etching on source resistance

    Publication Year: 1995 , Page(s): 1195 - 1196
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (188 KB)  

    Recessed gate microwave MESFET's and MODFET's have a recessed but unmetallized length Lδ of the channel adjacent to the gate, whose resistance Rδ can significantly contribute to the source resistance Rs. The ratio Rδ/R s can be determined using common test structures View full abstract»

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  • 2D numerical investigation of the impact of compositional grading on the performance of submicrometer Si-SiGe MOSFET's

    Publication Year: 1995 , Page(s): 1039 - 1046
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (680 KB)  

    Computer simulation is used to establish the impact of design parameters on the subthreshold characteristics, hot carrier injection, and high frequency performance of Si-SiGe FET's. The results indicate that by fully grading the Ge content in the channel of a MOSFET, short channel effects are reduced and high frequency performance is improved as compared to devices with uniform Ge channels. A cutoff frequency of 38 GHz and a maximum frequency of oscillation of 160 GHz are predicted for fully graded p-channel MOSFET's with 0.25 μm gate lengths. Energy balance simulation reveals that hot carrier injection at the Si-SiO2 interface is considerably suppressed if a fully graded channel is employed View full abstract»

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  • Electro-optic imaging of internal fields in (111) GaAs photoconductors

    Publication Year: 1995 , Page(s): 1081 - 1085
    Cited by:  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (304 KB)  

    The nonuniform electric field in a surface (111) GaAs photoconductor was imaged for the first time using the electro-optic effect of the device itself. The technique used a mode-locked 1.06 μm laser with 150 ps pulses to transiently probe the electric field profile at various times following application of a synchronized pulsed voltage bias View full abstract»

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  • Performance and reliability improvements in poly-Si TFT's by fluorine implantation into gate poly-Si

    Publication Year: 1995 , Page(s): 1106 - 1112
    Cited by:  Papers (7)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (604 KB)  

    High-performance and high-reliability TFT's have been obtained using a fluorine ion implantation technique. The fluorine implantation into the gate poly-Si of TFT caused a positive Vth shift, increased the ON current, and decreased the leakage current significantly. Our investigation indicates that the Vth shift originates from negative charges generated in the gate oxide by the fluorine implantation. The improvement of drain current is attributed to fluorine passivation of trap states in the poly-Si and to a modulation of offset potential due to the same negative charges under the offset region. Furthermore, high immunity against the -BT stress and TDDB of the gate oxide was achieved by the fluorine implantation. It is considered that the strong Si-F bonds created by the fluorine implantation raise the stress immunity View full abstract»

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  • A new approach to modeling the substrate current of pre-stressed and post-stressed MOSFET's

    Publication Year: 1995 , Page(s): 1113 - 1119
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (664 KB)  

    In this paper, we propose a closed form expression of a new and accurate analytical substrate current model for both pre-stressed and post-stressed MOSFET's. It was derived based on the concept of effective electric field, which gives a more reasonable impact ionization rate in the lucky-electron model. This effective electric field, composed by two experimentally determined parameters, can be regarded as a result of nonlocal heating effects within devices. This model shows a significant improvement to the conventional local field model. One salient feature of the present model is that it allows us to characterize the time evolution of the substrate current of stressed MOSFET's for the first time. Experimental verification for a wide variety of MOSFET's with effective channel lengths down to 0.3 μm shows that the new model is very accurate and is feasible for any kind of MOS device with different drain structures. The present model can be applied to explore the hot carrier effect in designing submicrometer MOS devices with emphasis on the design optimization of a device drain engineering issue. In addition, the present model is well suited for device reliability analysis and circuit level simulations View full abstract»

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  • Bulk breakdown of high field silicon-dielectric systems

    Publication Year: 1995 , Page(s): 1156 - 1165
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1012 KB)  

    Preliminary results on bulk breakdown in high field silicon-dielectric systems are reported. In most cases the total breakdown of the above systems takes place by surface flashover. Bulk breakdown in high field semiconductor-dielectric systems is supposed to be produced only when one or more large filaments are developed in the bulk of the material due to a particular defect configuration. The characteristics of the bulk breakdown of the system are totally different from surface flashover. These differences are explained by the different physical nature of the two kinds of the breakdown of the system, one located in the material bulk and other at the semiconductor-dielectric interface View full abstract»

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  • Extraction of the InP/GaInAs heterojunction bipolar transistor small-signal equivalent circuit

    Publication Year: 1995 , Page(s): 1059 - 1064
    Cited by:  Papers (39)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (400 KB)  

    An extraction technique for determining the small-signal equivalent circuit model of an InP/GaInAs heterojunction bipolar transistor is presented. The equivalent circuit includes the extrinsic base collector capacitance and extrinsic base resistance. It is clearly indicated which elements are uniquely determined, and which elements are estimated View full abstract»

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  • A quasi-two-dimensional HEMT model for microwave CAD applications

    Publication Year: 1995 , Page(s): 1026 - 1032
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (604 KB)  

    A new quasi-two-dimensional HEMT model has been developed that solves the physical device equations in a more rigorous fashion than previously reported. The model incorporates a quantum mechanical description of the free electron concentration, self-consistently solving the Schrodinger and Poisson equations. The influence of traps and incomplete donor ionization are also included. The conventional one-dimensional charge-control approach is shown to be inadequate for HEMT's and is replaced by a two-dimensional version that more accurately describes the channel dynamics under normal bias conditions. This allows the simulation to accurately model pinch-off characteristics, which are essential for digital, power and low-noise device characterization. The scheme also includes a detailed energy transport model, avalanche breakdown and gate conduction terms. The highly efficient model is applied to the DC and microwave characterization of AlGaAs-GaAs and pseudomorphic HEMT's View full abstract»

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  • Implementation of nonlocal model for impact-ionization current in bipolar circuit simulation and application to SiGe HBT design optimization

    Publication Year: 1995 , Page(s): 1166 - 1173
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (664 KB)  

    A nonlocal characterization of impact-ionization current is implemented in a compact but physical bipolar transistor model for predictive circuit simulation. The charge-based model, which is applicable to SiGe-base HBT's as well as Si BJT's, provides at each bias point, including ones in quasisaturation, the electric field distribution E(x) in the epi-collector, and a simplified form of the energy-balance equation enables characterization of carrier temperature Te(x) from E(x). Numerical spatial integration of the Te -dependent ionization rate yields the impact-ionization current as post-processing in the model routine. The nonlocal model is verified by applications to two advanced bipolar (HBT and BJT) technologies in which the device breakdown voltages, which are underestimated by the local-field model, are predicted. The utility of the nonlocal model in assessing design tradeoffs involving impact ionization (i.e., device breakdown versus circuit performance) is demonstrated by simulations based on the two mentioned technologies View full abstract»

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  • Study on hydrogenation of polysilicon thin film transistors by ion implantation

    Publication Year: 1995 , Page(s): 1134 - 1140
    Cited by:  Papers (7)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (560 KB)  

    Hydrogenation of polysilicon (poly-Si) thin film transistors (TFT's) by ion implantation has been systematically studied. Poly-Si TFT performance was dramatically improved by hydrogen ion implantation followed by a forming gas anneal (FGA). The threshold voltage, channel mobility, subthreshold swing, leakage current, and ON/OFF current ratio have been studied as functions of ion implantation dose and FGA temperature. Under the optimized conditions (H+ dose of 5×1015 cm-2 and FGA temperature at 375°C), NMOS poly-Si TFT's fabricated by a low temperature 600°C process have a mobility of ~27 cm 2/V·s, a threshold voltage of ~2 V, a subthreshold swing of ~0.9 V/decade, and an OFF-state leakage current of ~7 pA/μm at VDS=10 V. The avalanche induced kink effect was found to be reduced after hydrogenation View full abstract»

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  • On the monotone finite difference schemes for energy transport models

    Publication Year: 1995 , Page(s): 1189 - 1192
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (348 KB)  

    The success of numerical simulation is determined by the stability of discretization schemes. The existing schemes for the energy transport (hydrodynamic-like) models are examined in terms of the maximum principle. Improved finite difference schemes are developed for the current continuity and energy balance equations View full abstract»

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  • Development of an integrated high speed silicon PIN photodiode sensor

    Publication Year: 1995 , Page(s): 1093 - 1099
    Cited by:  Papers (18)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (604 KB)  

    A silicon integrated PIN photodiode sensor, combined with a bipolar IC on same substrate (that is, a PIN photo integrated circuit sensor: PIN-PICS), was developed by employing a high resistive P-- epitaxial layer on a P+ substrate for creating a high speed and high optical responsivity PIN photodiode. We fabricated this device based on two special techniques: (1) the PIN photodiode is formed on a P--/P+ substrate structure and isolated from bipolar components by the combination of a P--well and a trench isolation, and (2) bipolar components are formed by the doubly diffused buried layer of the P--well and the N+ collector wall. All of these components, such as npn and pnp transistors, were arranged within the lightly doped P--well regions. From several kinds of trial samples, the following results were obtained. The PIN photodiode with 0.145 mm2 active area indicated 680 MHz for cutoff frequency at 10 V bias with 830 mn radiation. In the case of 20 V bias, this value exceeded 1.5 GHz. This PIN-PICS was applied to a 10 Mbit/s burst mode compatible optical monolithic receiver and a transimpedance amplifier, and it has shown the expected results View full abstract»

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  • Thermal coupling in 2-finger heterojunction bipolar transistors

    Publication Year: 1995 , Page(s): 1033 - 1038
    Cited by:  Papers (32)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (556 KB)  

    We have previously analyzed the collapse phenomenon in heterojunction bipolar transistors (HBT's) when the mutual couplings among the transistor fingers are negligible. In this investigation, we derive the collapse loci equations in 2-finger HBT's in the presence of thermal coupling. It is found that the collapse loci equations are closely linked to a thermal instability condition best determined from the transistor regression characteristics. Unlike the previous derivation assuming zero thermal coupling, the collapse loci equations derived here are different depending on whether the HBT is driven by constant base current or constant base voltage bias View full abstract»

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  • Characteristics of SiNx/InP/In0.53Ga0.47 As/InP heterostructure insulated gate (HIG)FET's with an In2 S3 interface control layer

    Publication Year: 1995 , Page(s): 1197 - 1199
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB)  

    InP/InGaAs HIGFET's with SiNx as gate insulator have been fabricated for the first time. An In2S3 interface control layer (ICL) is used to reduce trap states at the InP/SiNx interface. The ICL HIGFET's show excellent drain I-V characteristics and allows large gate swings (±5 V) with negligible (<1 nA) gate leakage View full abstract»

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  • Space charge and light generation in SrS:Ce thin film electroluminescent devices

    Publication Year: 1995 , Page(s): 1086 - 1092
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (604 KB)  

    Transient light and charge-voltage measurements on SrS and SrS:Ce thin film electroluminescent devices have been carried out with triangular voltage bursts after illumination. The observations indicate that the trailing edge emission is due to electrons which are emitted from the anodic interface as soon as the field there changes sign and recombine effectively with ionized Ce atoms. From charge-voltage measurements the space charge in the phosphor layer is estimated to be two times higher for the Ce doped sample. Due to this sample charge the field in the phosphor layer of the SrS:Ce devices decreases dramatically from the cathodic toward the anodic interface. If the field at the anodic interface is close to zero, efficient light emission will arise from recombination of electrons with ionized Ce atoms in this region View full abstract»

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IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego