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Design & Test of Computers, IEEE

Issue 2 • Date Summer 1995

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Displaying Results 1 - 10 of 10
  • Introduction to the scheduling problem

    Publication Year: 1995 , Page(s): 60 - 69
    Cited by:  Papers (31)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (947 KB)  

    Scheduling-a central task in high-level synthesis-involves determining the execution order of operations in a behavioral description. After introducing the scheduling problem, this paper describes four scheduling algorithms commonly used to solve it.<> View full abstract»

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  • An overview of test synthesis tools

    Publication Year: 1995 , Page(s): 8 - 15
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (648 KB)  

    The two types of tools now commercially available implement the basic elements of first synthesis differently. Selecting among various gate- and RT-level tools requires a careful evaluation considering issues like desired circuit quality, methodology circuit area, and integration View full abstract»

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  • Single clock partial scan

    Publication Year: 1995 , Page(s): 24 - 31
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (568 KB)  

    Existing partial-scan designs use a separate scan clock to simplify scan flip-flop selection and test generation methods. Such designs require multiple clock trees and create clock-signal routing problems that, in general, require tight control of clock skew. The author examines using the system clock for the scan operation and includes experimental results based on ISCAS89 benchmark circuits View full abstract»

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  • Multifrequency analysis of faults in analog circuits

    Publication Year: 1995 , Page(s): 70 - 80
    Cited by:  Papers (38)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (788 KB)  

    Testability analysis of analog circuits in the presence of soft, large-deviation, and hard faults greatly facilitates production of testable systems. The authors analyze these faults by observing their symptoms at the circuit's output, an approach that uses the same test methodology to analyze all three fault types. Their algorithm indicates the set of adequate test frequencies and nodes that incr... View full abstract»

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  • Testability implications of performance driven logic synthesis

    Publication Year: 1995 , Page(s): 32 - 39
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (592 KB)  

    Retiming improves performance but also increases test generation time and decreases fault coverage. Research conducted at Carnegie Mellon and McGill Universities attempts to explain the impact of retiming on the testability of sequential logic circuits. A novel test preservation theorem suggests a powerful way to decrease the test generation cost of retimed circuits. The authors also discuss a rec... View full abstract»

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  • A business view of networks

    Publication Year: 1995 , Page(s): 3 - 4
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (180 KB)  

    It goes without saying that graph theory plays a big role in EDA. While we take this for granted in engineering EDA solutions, the business world, EDA and otherwise, has not, for the most part, considered the firm as part of a network. However, especially in high technology, the network form of business organization is an integral part of the business model. This article discusses the network view... View full abstract»

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  • Synthesizing circuits with implicit stability constraints

    Publication Year: 1995 , Page(s): 16 - 23
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (580 KB)  

    Test synthesis constraints embody conditions that a circuit must meet to be fully testable. Algorithms similar to those of automatic test pattern generation transform the circuit and repair rule violations corresponding to the constraints. This form of test synthesis occurs early in the design process; allowing effective investigation of performance and area trade-offs. A prototype implementation ... View full abstract»

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  • IEEE Std 1149.1: where are we? where from here?

    Publication Year: 1995 , Page(s): 53 - 59
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (612 KB)  

    The authors discuss the status and celebrate the success of IEEE Std 1149.1, hoping to motivate discussion and action that will encourage further development of boundary scan-based testing. They offer the insight of experienced implementers of the standard working in competitive business environments View full abstract»

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  • Microprocessor IDDQ testing: a case study

    Publication Year: 1995 , Page(s): 42 - 52
    Cited by:  Papers (28)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (824 KB)  

    The author describe their incorporation of IDDQ testing into the design of the PA-7100LC PA-RISC microprocessor. They also discuss design guidelines, measurement techniques, results after fabrication and volume production, and suggested improvement. Their 900,000-transistor custom design supports IDDQ testing to ensure high quality without compromising 100-MHz-plus performanc... View full abstract»

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  • IDDQ design and test advantages propel industry

    Publication Year: 1995 , Page(s): 40 - 41
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (144 KB)  

    The IDDQ test method measures the quiescent power supply current of CMOS ICs for select test vectors, or logic states, and provides a clear indication of defects, failure mechanisms, and many types of design errors. Underlying this type of test are design principles that inherently provide high defect coverage, as well as diagnosis capability and physical localization. The ability of I... View full abstract»

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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Editor-in-Chief
Krishnendu Chakrabarty