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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 5 • May 1995

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Displaying Results 1 - 14 of 14
  • Circuit-level dictionaries of CMOS bridging faults

    Publication Year: 1995, Page(s):596 - 603
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (666 KB)

    The contribution of this paper on the diagnosis (fault location) of CMOS bridging faults is threefold: First, the traditional fault dictionary (referred to as the full dictionary in this paper) is evaluated at the circuit level using a mixed-mode fault simulator. The fault set consists of randomly-generated gate input/output bridging faults. By using mixed-mode gate- and electrical-level detection... View full abstract»

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  • Fault coverage estimation by test vector sampling

    Publication Year: 1995, Page(s):590 - 596
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (691 KB)

    We have developed a new statistical technique for estimating delay fault coverage in combinational circuits. True value simulation is performed for a sample of vector pairs chosen randomly from the test set. Transition probabilities and observabilities are estimated from the simulation data. These allow us to estimate fault detection probabilities per vector pair. Fault models considered are the t... View full abstract»

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  • Delay-fault testability preservation of the concurrent decomposition and factorization transformations

    Publication Year: 1995, Page(s):582 - 590
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (859 KB)

    In this paper, we study the testability preservation of the concurrent decomposition and factorization transformations under several delay-fault testing constraints. We show that all transformations, except dual extraction of multiplexor structures, preserve testability with respect to a general Robust Path-Delay-Fault (RPDF) test set, Validatable Nonrobust (VNR) delay-fault test set, and Delay Ve... View full abstract»

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  • Path-delay-fault testable nonscan sequential circuits

    Publication Year: 1995, Page(s):576 - 582
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (660 KB)

    In this paper we show that any finite state machine can be implemented by a fully path-delay-fault testable nonscan sequential circuit. Synthesis methods are proposed, which use a one-hot encoding of states, a special circuit structure and at most one additional input. Combined with existing synthesis techniques for delay-fault testable combinational circuits, these methods can produce nonscan seq... View full abstract»

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  • Open faults in BiCMOS gates

    Publication Year: 1995, Page(s):567 - 575
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (834 KB)

    Opens in BiCMOS structures are analyzed here. It is shown that some opens cannot be detected by stuck-fault or other functional tests, since some transistors in BiCMOS gates do not affect the logical function of the gate. A switch-level model for CMOS circuits is extended to include bipolar devices. With this switch-level model, opens that cannot be detected by stuck-faults or other functional tes... View full abstract»

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  • Efficient linear circuit analysis by Pade approximation via the Lanczos process

    Publication Year: 1995, Page(s):639 - 649
    Cited by:  Papers (727)  |  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (796 KB)

    In this paper, we introduce PVL, an algorithm for computing the Pade approximation of Laplace-domain transfer functions of large linear networks via a Lanczos process. The PVL algorithm has significantly superior numerical stability, while retaining the same efficiency as algorithms that compute the Pade approximation directly through moment matching, such as AWE and its derivatives. As a conseque... View full abstract»

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  • Test embedding with discrete logarithms

    Publication Year: 1995, Page(s):554 - 566
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1284 KB)

    When using Built-In Self Test (BIST) for testing VLSI circuits, a major concern is the generation of proper test patterns that detect the faults of interest. Usually a linear feedback shift register (LFSR) is used to generate test patterns. We first analyze the probability that an arbitrary pseudo-random test sequence of short length detects all faults. The term short is relative to the probabilit... View full abstract»

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  • 3-D numerical modeling of thermal flow for insulating thin film using surface diffusion

    Publication Year: 1995, Page(s):631 - 638
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (559 KB)

    This paper presents a three-dimensional (3-D) numerical surface diffusion model of BPSG glass flow of surface tension. The analysis region is divided into small cubic cells. Material surface is described as an equi-concentration (equi-existence rate) area which is obtained by linear interpolation between the cells. 3-D surface curvature is defined as the ratio of the increment of surface area to t... View full abstract»

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  • Reductions in quality caused by uneven fault coverage of different areas of an integrated circuit

    Publication Year: 1995, Page(s):603 - 607
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (453 KB)

    This paper addresses problems associated with the production and interpretation of traditional fault coverage numbers. In particular, the issue of nonuniform distribution of detected faults is addressed, It is shown that when any degree of defect clustering occurs in the IC fabrication process, there is a very big difference in final quality between covering the chip evenly all over and leaving pa... View full abstract»

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  • Considering testability at behavioral level: use of transformations for partial scan cost minimization under timing and area constraints

    Publication Year: 1995, Page(s):531 - 546
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1452 KB)

    We address the problem of transforming a behavioral specification so that synthesis of a testable implementation from the new specification requires significantly less area and partial scan cost than synthesis from the original specification. The proposed approach has three components: a library of relevant transformation mechanisms, an objective function, and an optimization algorithm. The most e... View full abstract»

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  • Analog checkers with absolute and relative tolerances

    Publication Year: 1995, Page(s):607 - 612
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (537 KB)

    The design of checkers aimed at the concurrent test of analog and mixed-signal circuits is considered in this paper. These checkers can on-line test duplicated and fully differential analog circuits. The test approach is based on exploiting the inherent redundancy of these circuits which results in the use of a code for the analog signals. The analog code is monitored by the checkers. An error sig... View full abstract»

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  • Controllable self-checking checkers for conditional concurrent checking

    Publication Year: 1995, Page(s):547 - 553
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (582 KB)

    Controllable self-checking (CSC) checkers can be included into concurrent checking schemes where only a subset of code words will be checked for correctness. A CSC checker can have four different working modes, depending on the scheme in which it operates. The checker can work in the system mode as well as in a test mode. In both modes the checker can either perform its usual check function or sup... View full abstract»

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  • Graph-based output phase assignment for PLA minimization

    Publication Year: 1995, Page(s):613 - 622
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (880 KB)

    A graph-based approach to finding near-optimal output phase assignments for PLA minimization is presented. A distinctive feature of the approach is that it exploits the necessary and sufficient conditions to reduce the number of product terms needed for PLA implementation and permits the use of existing graph algorithms to solve the PLA output phase optimization problem. The work is based on the t... View full abstract»

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  • A replication cut for two-way partitioning

    Publication Year: 1995, Page(s):623 - 630
    Cited by:  Papers (23)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (666 KB)

    Graph partitioning is crucial in multiple-chip design, floorplanning and mapping large logic networks into multiple FPGA's. Replication logic can be used to improve the partitioning. Given a network G with only two-pin nets and a pair of nodes s and t to be separated, we introduce a replication graph and an O(mn log(n2/m)) algorithm for optimum partitioning with replication and without ... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu