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Solid-State Circuits, IEEE Journal of

Issue 5 • Date May 1995

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Displaying Results 1 - 16 of 16
  • Resistive interpolation biasing: a technique for compensating linear variation in an array of MOS current sources

    Page(s): 595 - 598
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    A new technique called resistive interpolation biasing for accurately biasing a large number of analog cells on a VLSI chip is presented. Variations in oxide thickness, mobility, doping concentration, etc., cause inaccuracies in current ratios of two identically biased transistors if they are placed sufficiently far apart on a chip. The proposed technique compensates for these inaccuracies without using any sampling or switching. The technique has been verified using a 2 μm n-well CMOS process. Measurements show a factor of 3 improvement in terms of current ratio accuracy when the resistive interpolation technique is used. The circuit can be implemented with a small chip area and low power dissipation. This technique finds applications where extensive current duplication over a large area is required (e.g., analog memories, D/A converters, continuous-time filters, imaging arrays, neural networks, and fuzzy logic systems) View full abstract»

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  • A low supply voltage high PSRR voltage reference in CMOS process

    Page(s): 586 - 590
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    This paper describes a bandgap voltage reference circuit that operates with a 3 V power supply and is compatible with a digital CMOS process. The use of a simple circuit topology results in a small silicon area of 0.07 mm2, a power consumption of 1 mW and a high power supply rejection over a wide frequency band. The circuit realizes a temperature coefficient of 85 ppm/°C and a standard deviation of 20 mV without trimming View full abstract»

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  • Energy consumption modeling and optimization for SRAM's

    Page(s): 571 - 579
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    The recent trends in portable computing technologies have established the need for energy efficient design strategies. To achieve minimum energy design goals, system designers need a technique to accurately model the energy consumption of their design alternatives without performing a full physical design and full-circuit simulation. This paper presents and compares five approaches for modeling the energy consumption of CMOS circuits. These five modeling approaches have been chosen to represent the various levels of model complexity and accuracy found in the current literature. These modeling approaches are applied to the energy consumption of SRAM's to provide examples of their use and to allow for the comparison of their modeling qualities. It was found that a mixed characterization model-using a CV2 prediction for digital subsections and fitted simulation results for the analog subsections-is satisfactory (within ±1 process variation) for predicting the absolute energy consumed per cycle. This same model is also very good (within 2%) for predicting an optimum organization for the internal structures of the SRAM. Several common architectures and circuit designs for SRAM's are analyzed with these models. This analysis shows that global, rather than local improvements, produce the largest energy savings View full abstract»

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  • Novel switched current source for increasing output signal edge steepness of current switches without generating large overshoot

    Page(s): 612 - 615
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    Shortly switching off the current supplied to a current switch improves edge steepness and reduces overshoot of the output current. This allows higher input voltage swing to achieve yet steeper edges while keeping overshoot reasonably small. An example shows reduction of rise time and fall time to 50% and 70%, respectively View full abstract»

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  • A low-voltage switched-current delta-sigma modulator

    Page(s): 599 - 603
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    This paper presents the design of a fully differential switched-current delta-sigma modulator using a single 3.3-V power-supply voltage. At system level, we tailor the modulator structure considering the similarity and difference of switched-capacitor and switched-current realizations. At circuit level, we propose a new switched-current memory cell and integrator with improved common mode feedback, without which low power-supply-voltage operation would not be possible. The whole modulator was implemented in a 0.8-μm double-metal digital CMOS process. It occupies an active area of 0.53×0.48 mm2 and consumes a current of 0.6 mA from a single 3.3-V power supply. The measured dynamic range is over 10 b View full abstract»

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  • A hybrid analog and digital VLSI neural network for intracardiac morphology classification

    Page(s): 542 - 550
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    Current Implantable Cardioverter Defibrillators (ICD's) use timing based decision trees for cardiac arrhythmia classification. Timing alone does not distinguish all rhythms for all patients. Hence, more computationally intensive morphology analysis is required for complete diagnosis. An analog VLSI neural network has been designed and tested to perform cardiac morphology classification tasks. Analog techniques were chosen to meet the strict power and area requirements of the implantable system while incurring the design difficulties of noise, drift and offsets inherent in analog approaches. The robustness of the neural network architecture however, to a large extent, overcomes these inherent shortcomings of the analog approach. The network is a 10:6:3 multilayer perceptron with on chip digital weight storage. The chip also includes a bucket brigade input to feed the Intracardiac Electrogram (ICEG) to the network and a Winner Take All circuit for converting classifications to a binary representation. The training system trained the network in loop and included a commercial implantable defibrillator in the signal processing path. The system has successfully distinguished two arrhythmia classes on a morphological basis for seven different patients with an average of 95% true positive and 97% true negative detections for the dangerous rhythm. The chip was implemented in 1.2 μm CMOS and consumes less than 200 nW maximum average power from a 3 V supply in an area of 2.2×2.2 mm2 View full abstract»

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  • A 32-channel charge readout IC for programmable, nonlinear quantization of multichannel detector data

    Page(s): 533 - 541
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    A Charge Readout Integrated Circuit (CRIC) which converts detector charges to digital codes is described. The CRIC provides 32 channels of circuitry needed to form charge-to-digital converters having a total dynamic range of 17 b comprised of 4 b of pre-amp gain control and a conversion range of 13 b. Each channel includes a switched-capacitor integrator, a double-sampling amplifier, a sampling comparator, and a 12-b digital latch, forming a pipeline from which a new conversion result is readout every 50 μs. The data conversion scheme implements a programmable compression curve, which is stored as a lookup table in an off-chip, digital memory. In addition to the lookup table, data conversion requires an off-chip digital-to-analog converter, both of which may be shared by any number of CRIC's. The CRIC was fabricated using a 3-μm, n-well BiCMOS process, and occupies a die area of 5.1 mm×7.5 mm. It operates at 10 MHz, consumes 440 mW from ±5-V supplies, and has a demonstrated input-referred noise performance of 2.2 μV r.m.s., i.e., 1400 e- on 100 pF of shunt capacitance View full abstract»

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  • An unconditionally stable two-stage CMOS amplifier

    Page(s): 591 - 594
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (268 KB)  

    This paper describes a two-stage CMOS amplifier that is stable for any capacitive load. This is achieved through the use of an optimized cascoded compensation topology. A new level shifting technique allows independent optimization of drive capability, noise and systematic offset voltage. The circuit is 0.1 mm2 in a 2 μm technology and has a quiescent current consumption of 110 μA View full abstract»

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  • Design and performance of multistage GaAs dynamic logic

    Page(s): 580 - 585
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    GaAs Two-Phase Dynamic FET Logic (TDFL) circuits are capable of extremely low power dissipation (20 nW/MHz/gate), high speed (1 GHz), and are compatible with static GaAs logic families. This paper demonstrates that TDFL can be modified to execute two or three stages of logic in one clock phase. This extension provides extremely high functional complexity per gate that can be used to reduce power dissipation, reduce latency, and increase circuit density in both sequential and computationally-oriented applications. The performance of these gates was demonstrated by E/D MESFET IC test circuits fabricated by a digital IC foundry. A one clock cycle, 8-b carry-lookahead adder operated at 350 MHz with only 1.1 mW of power dissipation View full abstract»

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  • A static power saving TTL-to-CMOS input buffer

    Page(s): 616 - 620
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (364 KB)  

    This paper describes a TTL-to-CMOS input buffer that has no static power consumption for the typical TTL voltage level. The input buffer utilizes a feedback configuration to eliminate static power consumption that renders hysteresis characteristic. The hysteresis characteristic is equivalent to that of a Schmitt trigger and thus provides good noise immunity. A prototype circuit was implemented in a 0.8 μm CMOS process, and the through current is measured to be only 8.9 μA and 11.7 μA for the input of 0.8 V and 2.2 V (the worst case TTL level), respectively. The input buffer gives full-swing output upto 170 MHz when driving a minimum sized inverter with the worst case TTL level according to SPICE simulation View full abstract»

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  • Precise final state determination of mismatched CMOS latches

    Page(s): 607 - 611
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB)  

    The effect on the metastability of mismatched FET parameters and load capacitances of CMOS latch/flip-flop is analyzed. Theoretical analysis based on small signal devices are provided. From this study we show that the final state depends on both initial voltages and latch mismatches. A novel method using state diagrams is proposed. On the state diagrams obtained by transient analysis of the latch, a straight line can be approximately drawn that defines two semi-planes. This straight line (the metastable line) determines precisely the final latch state, and gives a very good insight about the mismatches which exist in the latch. Several SPICE simulation results are shown for matched/mismatched flip-flops. They agree well with the theoretical ones View full abstract»

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  • A 10-b 20-Msample/s low-power CMOS ADC

    Page(s): 514 - 521
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    A single-ended input but internally differential 10 b, 20 Msample/s pipelined analog-to-digital converter (ADC) is demonstrated with 4 mW per stage using a single 5 V supply. The prototype ADC made of an input sample and hold (S/H) plus 8 identical unscaled pipelined stages consumes 50 mW including power consumed by a bias generator and two internal buffer amplifiers driving common-mode bias lines. Key circuits developed for this low-power ADC are a dynamic comparator with a capacitive reference voltage divider that consumes no static power, a source-follower buffered op amp that achieves wide bandwidth using large input devices, and a self-biased cascode biasing circuit that tracks power supply variation. The ADC implemented using a double-poly 1.2 μm CMOS technology exhibits a DNL of ±0.65 LSB and a SNDR of 54 dB while sampling at 20 MHz. The chip die area is 13 mm2 View full abstract»

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  • A CMOS transistor-only 8-b 4.5-Ms/s pipelined analog-to-digital converter using fully-differential current-mode circuit techniques

    Page(s): 522 - 532
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    Fully-differential current-mode circuit techniques are developed for the design of a pipelined current-mode analog-to-digital converter (IADC) in the standard CMOS digital processes. In the proposed IADC, the 1-b-per-stage architecture based on the reference nonrestoring algorithm is adopted. Thus large component ratios can be avoided and the linearity errors caused by device mismatches can be minimized. As one of the key subcircuits in the IADC, an offset-canceled high speed differential current comparator (CCMP) is proposed and analyzed. In the CCMP, the subtractions of offsets are performed in the current domain without floating capacitors. Moreover, the other key subcircuit, the current sample-and-hold amplifier (CSHA), is also developed to realize the pipeline architecture. An experimental chip for the proposed IADC has been fabricated in 0.8-μm n-well CMOS technology. Using a single 5-V power supply, the fabricated IADC can be operated at 4.5-Ms/s conversion rate with a signal-to-noise-and-distortion-ratio (SNDR) of 51 db (effective 8.2-b) for the input signal at 453 kHz. For 8-b resolution, the fabricated IADC can be operated at 4.5-Ms/s conversion rate with both differential nonlinearity (DNL) and integral nonlinearity (INL) below +/-0.6 LSB. The power consumption and the active chip area are 16 mW/b and 0.73 mm2/b, respectively View full abstract»

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  • Weak inversion charge injection in analog MOS switches

    Page(s): 604 - 606
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    The on-chip test circuit for examining the charge injection in analog MOS switches has been described in detail, and has been fabricated and characterized. Mixed-mode circuit and device simulations have been performed, creating excellent agreements not only with the experimental waveforms but also with the measured switch-induced error voltage. Further investigation of the experimental and simulated results has separated the charge injection into three distinct components: i) the channel charges in strong inversion; ii) the channel charges in weak inversion; and iii) the charges coupled through the gate-to-diffusion overlap capacitance. Important observations concerning the weak inversion charge injection have been drawn from the waveform of the current through the switched capacitor. In this work the channel charges in weak inversion have exhibited a 20% contribution to the switch-induced error voltage on a switched capacitor View full abstract»

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  • Novel high speed circuit structures for BiCMOS environment

    Page(s): 563 - 570
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    Novel high speed BiCMOS circuits including ECL/CMOS, CMOS/ECL interface circuits and a BiCMOS sense amplifier are presented. A generic 0.8 μm complementary BiCMOS technology has been used in the circuit design. Circuit simulations show superior performance of the novel circuits over conventional designs. The time delays of the proposed ECL/CMOS interface circuits, the dynamic reference voltage CMOS/ECL interface circuit and the BiCMOS sense amplifier are improved by 20, 250, and 60%, respectively. All the proposed circuits maintain speed advantage until the supply voltage is scaled down to 3.3 V View full abstract»

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  • Investigation of very fast and high-current transients in digital bipolar IC's using both a new compact model and a device simulator

    Page(s): 551 - 562
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    The design and optimization of high-speed integrated bipolar circuits requires accurate and physical transistor models. For this, an improved version of the compact model HICUM was developed. It is an extension of the small-signal model recently described to the large-signal (transient) case. The model, which takes into account emitter periphery and non-quasi-static (NQS) effects, is semi-physical, allowing the calculation of its elements for arbitrary transistor geometries from specific electrical and technological data. This is an important precondition for transistor optimization in a circuit and for worst case analysis. The model was verified for basic building blocks of high-speed digital circuits like emitter follower and current switch. For this, mixed-mode device/circuit simulation is used instead of measurements, since the latter would give too large errors for the fast transients of interest. It is demonstrated that-in contrast to the obsolete but frequently used SPICE Gummel/Poon model-the new HICUM is well suited for modeling very-high-speed transistor operation also at high current densities. Moreover, it is shown that at very fast transients the influence of NQS effects can no longer be neglected. As a practical application example, a high-speed E2CL circuit is simulated using the new model. The results show again that high-current models are very useful for designing IC's at maximum operating speed. This is because the optimum emitter size is often the minimum size, which is limited by high-current effects. Especially, in the case of current spikes (e.g., in emitter followers) it is difficult to find the optimum emitter size without having adequate transistor models View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan