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Electron Device Letters, IEEE

Issue 5 • Date May 1995

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Displaying Results 1 - 18 of 18
  • High quality SiO/sub 2//Si interfaces of poly-crystalline silicon thin film transistors by annealing in wet atmosphere

    Publication Year: 1995 , Page(s): 157 - 160
    Cited by:  Papers (18)  |  Patents (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (344 KB)  

    A new post-metallization annealing technique was developed to improve the quality of metal-oxide-semiconductor (MOS) devices using SiO/sub 2/ films formed by a parallel-plate remote plasma chemical vapor deposition as gate insulators. The quality of the interface between SiO/sub 2/ and crystalline Si was investigated by capacitance-voltage (C-V) measurements. An H/sub 2/O vapor annealing at 270/spl deg/C for 30 min efficiently decreased the interface trap density to 2.0/spl times/10/sup 10/ cm/sup -2/ eV/sup -1/, and the effective oxide charge density from 1/spl times/10/sup 12/ to 5/spl times/10/sup 9/ cm/sup -2/. This annealing process was also applied to the fabrication of Al-gate polycrystalline silicon thin film transistors (poly-Si TFT's) at 270/spl deg/C. In p-channel poly-Si TFT's, the carrier mobility increased from 60-400 cm/sup 2/ V/sup -1/ s/sup -1/ and the threshold voltage decreased from -5.5 to -1.7 V.<> View full abstract»

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  • A novel offset gated polysilicon thin film transistor without an additional offset mask

    Publication Year: 1995 , Page(s): 161 - 163
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (252 KB)  

    We have proposed a novel offset gated polysilicon TFT fabricated without an offset mask in order to reduce leakage current and suppress the kink effect. The photolithographic process steps of the new TFT device are identical to those of conventional non-offset structure TFT's and an additional mask to fabricate an offset structure is not required in our device. The new device has demonstrated a lower leakage current and a better ON/OFF current ratio compared with the conventional non-offset device. The novel TFT also exhibits a considerable reduction in the kink effect because a very thin film TFT may be easily fabricated due to the elimination of the contact over-etch problem.<> View full abstract»

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  • Thin polyoxide on the top of poly-Si gate to suppress boron penetration for pMOS

    Publication Year: 1995 , Page(s): 164 - 165
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (210 KB)  

    A method of using a thin oxide on the top of the poly-Si gate to getter fluorine for BF/sub 2//sup +/ in pMOS is proposed and demonstrated. Due to less amount of fluorine in the poly-Si as well as in the gate oxide, the boron penetration through the gate oxide is suppressed. The MOS capacitors fabricated by using this method show less shifts and distortion on C-V curves and better electrical characteristics.<> View full abstract»

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  • A novel optical accelerometer

    Publication Year: 1995 , Page(s): 166 - 168
    Cited by:  Papers (6)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (238 KB)  

    A novel accelerometer based on a PIN photo-detector and a micro-machined cantilever-beam-supported optical shutter with seismic mass has been designed, fabricated, and tested. Anisotropic wet etching of <110> orientation silicon in KOH is used to fabricate an optical shutter consisting of evenly spaced vertically etched slots. The shutter, which also constitutes the seismic mass of the accelerometer, is suspended by two cantilever beams. The special structure of the device and the high aspect ratio of the cantilever beams (7.5) permit freedom of the movement for the proof mass (the shutter) on the /spl plusmn/X axis only. The actual size of the device is 3/spl times/4 mm and its amplified output varies linearly from -3.6 V to +3.6 V for accelerations from -84 g to +84 g. The measured resonant frequency of the device is 3.2 KHz. A dual diode structure is chosen for the photo-detector to compensate for temperature drift and the amplified output voltage changes by less than 40 mV for a temperature variation from 25/spl deg/C to 50/spl deg/C.<> View full abstract»

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  • A bipolar load CMOS SRAM cell for embedded applications

    Publication Year: 1995 , Page(s): 169 - 171
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (307 KB)  

    This paper presents a new SRAM cell concept which offers cell scaling without requiring complicated, specialized processing technology. The proposed cell utilizes a bipolar transistor in an open-base (base is floating) configuration as a simple means of realizing a high impedance load element. The Bipolar Transistor Load (BTL) is designed such that its open base current (the holding current) is always large enough to compensate for the NMOS pull-down transistor leakage current. The load holding current and the pull-down transistor leakage current are based on the same physical mechanism, namely thermal generation, as a result the load exhibits current tracking properties over varying process and temperature conditions. The cell size is 72 μm2 with typical 0.8 μm design rules, which is about a 60% reduction as compared to a standard 6-T full CMOS cell. The operating properties of the BTL cell were studied analytically and characterized experimentally. The BTL SRAM module can be easily integrated as part of any CMOS process with minimal additional processing steps. View full abstract»

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  • Impact of fluorine incorporation in the polysilicon emitter of NPN bipolar transistors

    Publication Year: 1995 , Page(s): 172 - 174
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    We demonstrate that fluorine incorporation in the polysilicon emitter of NPN bipolar transistors significantly reduces the current gain h/sub fe/. The gain degradation can be related to a reduction of the barrier to hole transport at the poly-Si/mono-Si interface. In addition to a gain reduction, fluorinated-emitter transistors display lower base recombination currents (at low base-emitter biases) than nonfluorinated emitter devices, suggesting that fluorine passivates recombination centers in the emitter-base space charge region.<> View full abstract»

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  • A novel high-speed silicon MSM photodetector operating at 830 nm wavelength

    Publication Year: 1995 , Page(s): 175 - 177
    Cited by:  Papers (12)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (286 KB)  

    A novel high-speed silicon photodetector that operates at a wavelength of 830 nm is reported. It consists of a Metal-Semiconductor-Metal (MSM) detector that is fabricated on a 5-μm thick silicon membrane. The detector has a measured -3 dB bandwidth of 3 GHz at 10 V, which is almost one order of magnitude larger than the reported bandwidth of conventional silicon MSM detectors as measured at 830 nm. The DC responsivity is 0.17 A/W, corresponding to an internal quantum efficiency of 60.5% and an external quantum efficiency of 25.4%. The large bandwidth and good responsivity at the wavelength of interest, combined with its low operating voltage and compatibility with most silicon integrated circuit technologies, make this detector a promising candidate for monolithic optoelectronic receiver circuits for use in short distance optical communication systems and computer interconnects. View full abstract»

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  • Static random access memories based on resonant interband tunneling diodes in the InAs/GaSb/AlSb material system

    Publication Year: 1995 , Page(s): 178 - 180
    Cited by:  Papers (16)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (263 KB)  

    We have fabricated SRAM's based on resonant interband tunneling diodes in the InAs/AlSb/GaSb material system. The bistability and the switching principles are demonstrated. Numerical simulations of the memory characteristics of the SRAM cell are performed and used for comparing with experiments. Several key issues involving the applications of the device are also discussed.<> View full abstract»

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  • Investigation of the soft-write mechanism in source-side injection flash EEPROM devices

    Publication Year: 1995 , Page(s): 181 - 183
    Cited by:  Papers (4)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (274 KB)  

    The soft-write effect which occurs when reading the content of a source-side injection (SSI) flash EEPROM cell has been identified and thoroughly investigated. This effect is caused by an electron injection mechanism which has the same physical origin as the enhanced (or source-side) hot-electron injection that is used for fast flash EEPROM programming. A procedure for the prediction of the associated soft-write lifetime is proposed, subsequently applied to a state-of-the-art split-gate SSI cell, and found to be noncritical for a reliable device operation. Therefore, source and drain do not have to be interchanged during the read-out operation with respect to the programming operation, and the traditional forward read-out scheme can be maintained for SSI flash memories.<> View full abstract»

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  • Hole trapping, substrate currents, and breakdown in thin silicon dioxide films [ in FETs ]

    Publication Year: 1995 , Page(s): 184 - 186
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (277 KB)  

    Using oxide-trapped-charge sensing techniques on FET's after high-field Fowler-Nordheim-stress, anode hole injection is shown to be important only for gate voltages larger than /spl ap/7.6 V for either p- or n-channel devices with n+ poly-Si gates independent of oxide thickness. These results do not support popular models for thin oxide degradation and "intrinsic" breakdown based on hole trapping in the oxide layer at lower voltages.<> View full abstract»

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  • New method for lifetime evaluation of gate oxide damaged by plasma processing

    Publication Year: 1995 , Page(s): 187 - 189
    Cited by:  Papers (8)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (287 KB)  

    A quantitative model is proposed, clarifying the relationship between the charge-to-breakdown with constant current injection (Q/sub bd/) and the time-to-breakdown with constant-voltage stress (t/sub bd/) for gate oxides damaged by plasma processing. By including the dependence of Q/sub bd/ on the stress current density, one can predict the t/sub bd/ by means of counting the fraction of the lifetime expenditure; J/spl Delta/t/Q/sub bd/(J), where J is the current density at each period (/spl Delta/t) under constant-voltage stressing, until the sum of the ratio is unity. The results show good agreement for the oxides of MOS capacitors with different gate areas. This method is useful for projection of the oxide lifetime.<> View full abstract»

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  • A low cost and high current gain a-Si/c-Si heterojunction photoreceiver for large area optoelectronics integrated circuit applications

    Publication Year: 1995 , Page(s): 190 - 192
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (257 KB)  

    An integrated a-Si/c-Si heterojunction p-i-n/n-p-n photoreceiver with high current gain performance is reported. The operation mechanism and experimental results of the device are discussed in the letter. In comparison with other III-V compound photoreceivers, the developed device does not need an additional gate bias and shows its compatibility with the periphery circuit for optoelectronic integrated circuit (OEIC) applications.<> View full abstract»

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  • A novel /spl beta/-SiC/Si heterojunction backward diode

    Publication Year: 1995 , Page(s): 193 - 195
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (240 KB)  

    In this letter, a novel /spl beta/-SiC/Si heterojunction backward diode has been developed successfully. The developed new backward diode is somewhat different from a conventional one. The /spl beta/-SiC thin film was grown by a low pressure rapid thermal chemical vapor deposition (LP-RTCVD) using a SiH/sub 4/-C/sub 3/H/sub 8/-H/sub 2/ gas system. Its current-voltage characteristics under different operation temperatures (25-200/spl deg/C) have been measured. In addition, the curvature coefficient /spl gamma/ has also been calculated and it is found to be insensitive to temperature variation up to 180/spl deg/C. The operation temperature is the highest reported thus far, to our knowledge.<> View full abstract»

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  • Field effect real space transfer transistor

    Publication Year: 1995 , Page(s): 196 - 198
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (278 KB)  

    We report demonstration of the first field effect real space transfer transistor (FERST), a gated real space carrier transfer device. It is a dual output, multifunctional device which, depending on region of operation, demonstrates either of three characteristics: traditional FET transconductance, sign reversing transconductance, or dual output with near complimentary transconductances. Additionally, the FERST structure provides a new means for exploring the physics of real space transfer.<> View full abstract»

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  • Self-aligned GaAs MISFET's with a low-temperature-grown GaAs gate insulator

    Publication Year: 1995 , Page(s): 199 - 201
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (262 KB)  

    GaAs MISFET's with a low-temperature-grown (LTG) GaAs gate insulator and ion-implanted self-aligned source and drain n/sup +/ regions are demonstrated. The resistivity and breakdown field of the LTG GaAs insulator were not changed appreciably by implantation and 800/spl deg/C activation annealing. The gate leakage current remained very low at a value of approximately 1 μA per μm2 of gate area at 3 V forward gate bias. Because of the reduced source and drain resistance, the drain saturation current and the transconductance of self-aligned MISFET's increased more than twofold after ion implantation. View full abstract»

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  • A new functional optical-electrical switch using a multi-emitter heterojunction phototransistor

    Publication Year: 1995 , Page(s): 202 - 204
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (253 KB)  

    We propose a new functional optical-electrical switching device: a multi-emitter heterojunction photo-transistor (ME-HPT) using a multi-emitter heterojunction bipolar transistor (ME-HBT) structure. In this device, the collector current (I/sub C/) can be controlled by not only the incident radiant power (P/sub 0/) but also the voltage difference between emitters (V/sub EE/). We fabricated ME-HPT's using InGaAs/InP heterostructures and confirmed the normal operation. Using only one ME-HPT, we have successfully demonstrated a new functional optical-electrical switching operation, which can switch on only when both the electrical and optical signals are high.<> View full abstract»

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  • Si/Si/sub 1-x/Gex heterojunction bipolar transistors with high breakdown voltage

    Publication Year: 1995 , Page(s): 205 - 207
    Cited by:  Papers (7)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (298 KB)  

    Heterojunction bipolar transistors are desirable for microwave applications because a low base resistance can be achieved yielding high maximum frequency of oscillation. Here we report Si/Si/sub 1-x/Ge/sub x/ heterojunction bipolar transistors with high breakdown voltages and excellent small-signal microwave characteristics. The transistors structures were grown by molecular beam epitaxy and fabricated by a double-mesa process. Measured f/sub T/ and f/sub max/ were 10 and 22 GHz, respectively, for transistors with BV/sub CBO/ of 40 V.<> View full abstract»

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  • Novel p-JFET embedded in silicon radiation detectors that avoids preamplifier feedback resistor

    Publication Year: 1995 , Page(s): 208 - 210
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (281 KB)  

    The paper describes the design and the performance of an original p-channel JFET embedded in the collecting anode of a silicon radiation detector. The choice of a p-channel transistor, whose gate-to-channel junction is forward biased by the leakage current from the detector, avoids the preamplifier feedback resistor and performs a continuous dc reset of the collected charge. The reported design, fully compatible with the detector fabrication, makes the operation of the detector extremely simple, ensures the best charge collection capability and leads to improved charge resolution. The first detector produced with this type of transistor has a resolution of 27 electrons rms in the measurement of the collected charge at room temperature for a pixel active area of about 0.1 mm/sup 2/, and of 22 electrons rms at T=210 K.<> View full abstract»

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