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IEEE Transactions on Computers

Issue 5 • Date May 1995

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Displaying Results 1 - 17 of 17
  • Improved digital signature algorithm

    Publication Year: 1995, Page(s):729 - 730
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB)

    A digital signature algorithm is developed which is an improved version of the digital signature algorithm (DSA) proposed by the NIST (1991). The security of the improved version is the same as the original one while it benefits the signature signer and performs more efficiently View full abstract»

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  • Optimal 2-bit branch predictors

    Publication Year: 1995, Page(s):698 - 702
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    This paper presents an efficient technique to analyze finite-state machines to determine an optimal one for branch prediction. It also presents results from using this technique to determine optimal 4-state branch predictors for applications in the SPECS9 benchmark suite running on the IBM RS/6000. The paper concludes that the simple 2-bit counter is the only machine that performs consistently wel... View full abstract»

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  • Unidirectional bit/byte error control

    Publication Year: 1995, Page(s):710 - 714
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    This paper defines a new class of unidirectional errors, named t/1-unidirectional errors, which affect at most t bits confined to at most t bytes of the code word. Codes that are capable of detecting, locating and correcting t/1-unidirectional errors are presented. Lower bounds on the number of checkbits required for t/1-unidirectional error detection and location are also presented View full abstract»

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  • Equivalence proofs of some yield modeling methods for defect-tolerant integrated circuits

    Publication Year: 1995, Page(s):724 - 728
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    In this paper, two equivalence proofs of yield modeling methods for defect-tolerant integrated circuits (ICs) are presented. These proofs are generalizations of those found in Koren and Stapper (1989); one of the proofs presented in this paper is valid for any defect-tolerant IC, while the other one is valid for defect-tolerant ICs with two levels of hierarchy View full abstract»

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  • Frames: a simple characterization of permutations realized by frequently used networks

    Publication Year: 1995, Page(s):695 - 697
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    Rearrangeable multistage networks such as the Benes network realize any permutation, yet their routing algorithms are not cost-effective. On the other hand, there exist inexpensive routing algorithms for nonrearrangeable networks, but no simple technique exists to characterize all the permutations realized on these networks. This paper introduces the concept of frame and shows how it can be used t... View full abstract»

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  • A 3D skewing and de-skewing scheme for conflict-free access to rays in volume rendering

    Publication Year: 1995, Page(s):707 - 710
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    We extend a 2D linear skewed memory organization to 3D and introduce the associated de-skewing scheme designed to provide conflict-free access to projection rays of voxels for use in a volume rendering architecture. This is an application of a 3D linear skewing scheme which supports real-time axonometric projection from 26 primary orientations View full abstract»

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  • Efficient stack simulation for set-associative virtual address caches with real tags

    Publication Year: 1995, Page(s):719 - 723
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    Stack simulation is a powerful cache analysis approach to generate the number of misses and write backs for various cache configurations in a single run. Unfortunately, none of the previous work on stack simulation has efficient stack algorithm for virtual address caches with real tags (VIR-type caches). In this paper, we devise an efficient stack simulation algorithm for analyzing VIR-type caches... View full abstract»

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  • Design of space-optimal regular arrays for algorithms with linear schedules

    Publication Year: 1995, Page(s):683 - 694
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (896 KB)

    The problem of designing space-optimal 2D regular arrays for N×N×N cubical mesh algorithms with linear schedule ai+bj+ck, 1⩽a⩽b⩽c, and N=nc, is studied. Three novel nonlinear processor allocation methods, each of which works by combining a partitioning technique (gcd-partition) with different nonlinear processor allocation procedures (traces), are proposed to handle differe... View full abstract»

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  • The Mobius cubes

    Publication Year: 1995, Page(s):647 - 659
    Cited by:  Papers (115)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1032 KB)

    The Mobius cubes are hypercube variants that give better performance with the same number of links and processors. We show that the diameter of the Mobius cubes is about one half the diameter of the equivalent hypercube, and that the average number of steps between processors for a Mobius cube is about two-thirds of the average for a hypercube. We give an efficient routing algorithm for the Mobius... View full abstract»

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  • Adaptive unanimous voting (UV) scheme for distributed self-diagnosis

    Publication Year: 1995, Page(s):730 - 735
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    Distributed self-diagnosis approach proposed for multiprocessor systems is also effective for integrated circuit wafers containing a number of identical circuits. Here the testing of each node is based on the majority voting on the test results from itself and neighboring nodes. In this paper, we identify that the unanimous voting (UV) approach always outperforms the individual voting (IV) approac... View full abstract»

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  • Safety levels-an efficient mechanism for achieving reliable broadcasting in hypercubes

    Publication Year: 1995, Page(s):702 - 706
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    We consider a distributed broadcasting algorithm for injured hypercubes using incomplete spanning binomial trees. An injured hypercube is a connected hypercube with faulty nodes. The incomplete spanning binomial tree proposed in this paper is a useful structure for implementing broadcasting in injured hypercubes. It is defined as a sub-tree of a regular spanning binomial tree that connects all the... View full abstract»

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  • Optimal realization of any BPC permutation on K-extra-stage Omega networks

    Publication Year: 1995, Page(s):714 - 719
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    An N×N k-Omega network is obtained by adding k more stages in front of an Omega network. An N-permutation defines a bijection between the set of N sources and the set of N destinations. Such a permutation is said to be admissible to a k-Omega if N conflict-free paths, one for each source-destination pair defined by the permutation, can be established simultaneously. When an N-permutation is ... View full abstract»

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  • Delay-insensitive pipelined communication on parallel buses

    Publication Year: 1995, Page(s):660 - 668
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (696 KB)

    Consider a communication channel that consists of several subchannels transmitting simultaneously and asynchronously. As an example of this scheme, we can consider a board with several chips. The subchannels represent wires connecting between the chips where differences in the lengths of the wires might result in asynchronous reception. In current technology, the receiver acknowledges reception of... View full abstract»

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  • Effective hardware-based data prefetching for high-performance processors

    Publication Year: 1995, Page(s):609 - 623
    Cited by:  Papers (182)  |  Patents (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1408 KB)

    Memory latency and bandwidth are progressing at a much slower pace than processor performance. In this paper, we describe and evaluate the performance of three variations of a hardware function unit whose goal is to assist a data cache in prefetching data accesses so that memory latency is hidden as often as possible. The basic idea of the prefetching scheme is to keep track of data access pattern... View full abstract»

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  • A coordinated location policy for load sharing in hypercube-connected multicomputers

    Publication Year: 1995, Page(s):669 - 682
    Cited by:  Papers (7)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1204 KB)

    Uneven task arrivals in a hypercube-connected multicomputer may temporarily overload some nodes while leaving others underloaded. This problem can be solved or alleviated by load sharing (LS); that is, some of the tasks arriving at overloaded nodes, called overflow tasks, are transferred to underloaded nodes. One important issue in LS is to locate underloaded nodes to which the overflow tasks can ... View full abstract»

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  • Fast combinatorial RNS processors for DSP applications

    Publication Year: 1995, Page(s):624 - 633
    Cited by:  Papers (50)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (848 KB)

    It is known that RNS VLSI processors can parallelize fixed-point addition and multiplication operations by the use of the Chinese remainder theorem (CRT). The required modular operations, however, must use specialized hardware whose design and implementation can create several problems. In this paper a modified residue arithmetic, called pseudo-RNS is introduced in order to alleviate some of the R... View full abstract»

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  • Conflict-free access for streams in multimodule memories

    Publication Year: 1995, Page(s):634 - 646
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1036 KB)

    Address transformation schemes, such as skewing and linear transformations, have been proposed to achieve conflict-free access for streams with constant stride. However, this is achieved only for some strides. In this paper, we extend these schemes to achieve this conflict-free access for a larger number of strides. The basic idea is to perform an out-of-order access to a stream of fixed length. T... View full abstract»

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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org