IEEE Transactions on Computers

Issue 4 • Apr 1989

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Displaying Results 1 - 14 of 14
  • A near-optimal heuristic algorithm for single-flow routing

    Publication Year: 1989, Page(s):603 - 608
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (668 KB)

    The authors obtain a tighter lower bound on the street congestion of optimal realizations. Then a heuristic algorithm based on necessary and sufficient conditions of optimality is proposed. Although it cannot be guaranteed that this algorithm always generates optimal realizations, it indeed generates optimal realizations for all the 60 test instances with which they experimented. This algorithm is... View full abstract»

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  • Hardware algorithms for determining similarity between two strings

    Publication Year: 1989, Page(s):600 - 603
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    The author presents pipelined hardware algorithms with time complexity O(n+m) for determining between two character strings expressed as the length of the longest common subsequence of the given pair of strings. The algorithms use cellular architecture with simple basic cells and regular nearest-neighbor communication generally suitable for VLSI implementation. Two methods are pr... View full abstract»

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  • Multistep gradual rounding

    Publication Year: 1989, Page(s):595 - 600
    Cited by:  Papers (8)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    A value V is to be rounded to an arbitrary precision resulting in the value V". Conventional rounding technique uses one step to accomplish this. Multistep rounding uses several steps to round the value V to successively shorter precisions with the final rounding step producing the desired value V". This alternate rounding method is one way to implement with the... View full abstract»

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  • Fault-tolerant array processors using single-track switches

    Publication Year: 1989, Page(s):501 - 514
    Cited by:  Papers (106)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1124 KB)

    An array grid model based on single-track switches is proposed. A reconfigurability theorem is developed to provide the theoretical footing for novel reconfiguration algorithms for the fabrication-time and run-time processing. For fabrication-time yield enhancement, the problem of finding a feasible reconfiguration using global control can be reformulated as a maximum independent set problem. An e... View full abstract»

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  • Minimizability of random Boolean functions

    Publication Year: 1989, Page(s):593 - 595
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    The average number of prime k-cubes and essential k -cubes in an n-variable, single-output Boolean function has already been obtained combinationally. The authors show how the same quantities can be obtained geometrically, using the theory of random clumping and take an initial step in calculating, for k-cubes in the minimized form of a function. The authors com... View full abstract»

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  • A group-theoretic model for symmetric interconnection networks

    Publication Year: 1989, Page(s):555 - 566
    Cited by:  Papers (606)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1144 KB)

    The authors develop a formal group-theoretic model, called the Cayley graph model, for designing, analyzing, and improving such networks. They show that this model is universal and demonstrate how interconnection networks can be concisely represented in this model. It is shown that this model enables the authors to design networks based on representations of finite groups. They can then analyze th... View full abstract»

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  • Diagnosis and repair of memory with coupling faults

    Publication Year: 1989, Page(s):493 - 500
    Cited by:  Papers (31)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB)

    The problem of diagnosis and spare allocation for random-access memory (RAM) with coupling faults is addressed. A number of spare allocation algorithms for RAM with row and column redundancy have recently been proposed. These procedures, however, have been restricted to repair stuck-at faults. The authors examine both diagnosis and repair of coupling faults in RAMs utilizing spare rows and columns... View full abstract»

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  • On implementing large binary tree architectures in VLSI and WSI

    Publication Year: 1989, Page(s):526 - 537
    Cited by:  Papers (24)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (960 KB)

    The authors present an efficient scheme for the layout of large binary-tree architectures by embedding the complete binary tree in a two-dimensional array of processing elements. Their scheme utilizes virtually 100% of the processing elements in the array as computing elements; it also shows substantial improvements in propagation delay and maximum edge length over H-tree layouts. They shown that ... View full abstract»

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  • On the optimal design of multiple-valued PLAs

    Publication Year: 1989, Page(s):582 - 592
    Cited by:  Papers (37)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB)

    A description is given of the design and analysis of three types of multivalued PLAs (programmable logic arrays). Type 1 PLAs realize functions directly in the form of the max of min of literal functions and constants. In Type 2 PLAs, the body of the PLA is binary and the output is encoded as a multiple-valued logic value. Type 3 PLAs are the same as type 2 PLAs except for the use of 2-bit decoder... View full abstract»

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  • Reconfiguration of VLSI/WSI mesh array processors with two-level redundancy

    Publication Year: 1989, Page(s):547 - 554
    Cited by:  Papers (41)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (716 KB)

    Reconfiguration schemes for replacing faulty cells (processing elements) with spare cells are introduced for massive parallel rectangular mesh array processors with fine-grained cells. The authors introduce the concept of two-level redundancy as an effective way of using redundant units to reduce the complexity of reconfiguration control circuitry, to limit the length of connecting wires after rec... View full abstract»

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  • Cache memory organization to enhance the yield of high performance VLSI processors

    Publication Year: 1989, Page(s):484 - 492
    Cited by:  Papers (36)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (808 KB)

    The authors study the tolerance of defects faults in cache memories. They argue that, even though the major components of a cache are linear RAMs (random-access memories), traditional techniques used for fault/defect tolerance in RAMs may be neither appropriate nor necessary for cache memories. They suggest a scheme that allows a cache to continue operation in the presence of defective/faulty bloc... View full abstract»

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  • On the design of fault-tolerant two-dimensional systolic arrays for yield enhancement

    Publication Year: 1989, Page(s):515 - 525
    Cited by:  Papers (35)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (972 KB)

    The authors propose a unified approach to the design of the fault-tolerant systolic arrays incorporating design for testability, a testing scheme, a reconfiguration algorithm, time-complexity analysis of the proposed reconfiguration algorithm, and yield analysis. A main feature of the proposed designs is that multiple processing elements in a 2-D array can be tested simultaneously, thus reducing t... View full abstract»

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  • The de Bruijn multiprocessor network: a versatile parallel processing and sorting network for VLSI

    Publication Year: 1989, Page(s):567 - 581
    Cited by:  Papers (160)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1140 KB)

    It is shown that the binary de Bruijn multiprocessor network (BDM) can solve a wide variety of classes of problems. The BDM admits an N -node linear array, an N-node ring, (N-1)-node complete binary trees, ((3N/4)-2)-node tree machines, and an N-node one-step shuffle-exchange network, where N (=2 k, k an integer) is the tota... View full abstract»

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  • Modeling defect spatial distribution

    Publication Year: 1989, Page(s):538 - 546
    Cited by:  Papers (52)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (708 KB)

    The center-satellite model for describing the distribution of defects on wafers is discussed. This model assigns each defect to a cluster. The distribution of cluster centers on a wafer is one basic component of the model. The other basic component is the distribution of defects (satellites) about the cluster centers. Physical justification for the model is provided. Current yield models are quite... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org