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IEEE Transactions on Computers

Issue 3 • Date Mar 1989

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Displaying Results 1 - 17 of 17
  • Mesh computer algorithms for computational geometry

    Publication Year: 1989, Page(s):321 - 340
    Cited by:  Papers (46)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2076 KB)

    Asymptotically optimal parallel algorithms are presented for use on a mesh computer to determine several fundamental geometric properties of figures. For example, given multiple figures represented by the Cartesian coordinates of n or fewer planar vertices, distributed one point per processor on a two-dimensional mesh computer with n simple processing elements, Θ(n... View full abstract»

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  • Decoupling link scheduling constraints in multi-hop packet radio networks

    Publication Year: 1989, Page(s):455 - 458
    Cited by:  Papers (23)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    An aspect of the problem of constructing a minimal length link schedule for a PRN (packet radio network) is examined. Specifically, it is assumed that a PRN of unrestricted topology is given, including a set of users, a set of channels, a set of interference links, a frequency band assignment, and an initial link schedule. It is required that any link schedule satisfies two constraints. The first ... View full abstract»

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  • A systolic architecture for fast dense matrix inversion

    Publication Year: 1989, Page(s):449 - 455
    Cited by:  Papers (37)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    An array that inverts an n×n dense matrix in 5n-1 time units, including I/O time, is presented. The inversion algorithm consists of three phases and assumes that Gaussian elimination without pivoting can be applied. The array, which consists of 2n2-n simple processing elements, implements and overlaps the execution of all three phases w... View full abstract»

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  • A highly parallel algorithm for root extraction

    Publication Year: 1989, Page(s):443 - 449
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (600 KB)

    A parallel algorithm for extracting the roots of a polynomial is presented. The algorithm is based on Graeffe's method, which is rarely used in serial implementations, because it is slower than many common serial algorithms, but is particularly well suited to parallel implementation. Graeffe's method is an iterative technique, and parallelism is used to reduce the execution time per iteration. A h... View full abstract»

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  • Decentralized decision-making for task reallocation in a hard real-time system

    Publication Year: 1989, Page(s):341 - 355
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1224 KB)

    A decentralized task reallocation algorithm for hard real-time systems is developed and analyzed. The algorithm, which is fast and reliable, specifically considers deadlines of tasks, attempts to utilize all the nodes of a distributed system to achieve its objective, handles tasks in priority order, and separates policy and mechanism. An extensive performance analysis of the algorithm by means of ... View full abstract»

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  • Parallel sorting in a ring network of processors

    Publication Year: 1989, Page(s):458 - 464
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (660 KB)

    A parallel implementation of selection sorting algorithms is presented that uses a ring-connected array of processors, in which each processor has the same amount of memory. The scheme allows all processors to have the same amount of memory with a small fragmentation loss. Uniformity in the size of the memories provides advantages from the viewpoint of manufacture, maintenance, inventory, item pla... View full abstract»

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  • Dynamic testing strategy for distributed systems

    Publication Year: 1989, Page(s):356 - 365
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (984 KB)

    Fault diagnosis is treated as two distinct processes: fault discovery and dissemination of diagnostic information. Previous research determined what level of self-diagnosability a given set of test in a homogeneous system achieves, using a model in which only node failures occur and test coverage is complete. Adopting the same model, a new methodology is presented that minimizes the overhead assoc... View full abstract»

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  • Modeling and performance analysis of single-bus tightly-coupled multiprocessors

    Publication Year: 1989, Page(s):464 - 470
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (620 KB)

    A hierarchical stochastic queuing model is presented that consists of a set of processing elements (PEs) and a single queue/server pair representing the shared memory. The model takes into account not only global system behavior but also behavior of tasks on each processing element and probabilistic task migration among the PEs. It is shown that through the use of repeated aggregation each PE can ... View full abstract»

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  • Formal verification of fault tolerance using theorem-proving techniques

    Publication Year: 1989, Page(s):366 - 376
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1068 KB)

    A formal verification system based on the use of automated reasoning techniques is described to validate fault tolerance. An extended Petri net representation, called a flow net, is described together with the theorem-proving implementation of a rule-based system for manipulating system descriptions. Examples taken from the literature are used to illustrate the representation and the capabilities ... View full abstract»

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  • On mapping algorithms to linear and fault-tolerant systolic arrays

    Publication Year: 1989, Page(s):470 - 478
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB)

    A simple mapping technique is developed to design systolic arrays with limited I/O capability. The technique is used to improve systolic algorithms for some matrix computations on linearly connected arrays of PEs (processor elements) with constant I/O bandwidth. The important features of these designs are modularity with constant hardware in each PE, few control lines, simple data-input/output for... View full abstract»

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  • An interpolating memory unit for function evaluation: analysis and design

    Publication Year: 1989, Page(s):377 - 384
    Cited by:  Papers (20)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (644 KB)

    A technique for the evaluation of a general continuous function f(x) is presented, and the design of an interpolating memory as an implementation of the technique is described. The technique partitions the domain of f(x) into segments and defines an interpolating (or approximating) function for each. The implementation is a memory subsystem that holds the parame... View full abstract»

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  • The PMC system level fault model: cardinality properties of the implied faulty sets

    Publication Year: 1989, Page(s):478 - 480
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB)

    One aspect of the PMC system level fault model, the properties of the implied faulty sets, is considered. For τ-diagnosable systems that have at most τ faulty units, lower bounds on the cardinality of the maximal implied faulty sets are given. Then it is shown that these bounds are greatest lower bounds, and it is indicated how these results can be used in diagnosis algorithms View full abstract»

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  • Fault-tolerant routing in multistage interconnection networks

    Publication Year: 1989, Page(s):385 - 393
    Cited by:  Papers (31)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (900 KB)

    The fault tolerance of multiprocessor systems with multistage interconnection networks under multiple faults in the network is studied. The fault tolerance is analyzed with respect to the criterion of dynamic full access (DFA) property of the processors in the system. A characterization of multiple faults in the Omega network is introduced and used to develop simple tests for the DFA capability un... View full abstract»

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  • Parallel testing for pattern-sensitive faults in semiconductor random-access memories

    Publication Year: 1989, Page(s):394 - 407
    Cited by:  Papers (30)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1108 KB)

    A design strategy is presented for efficient and comprehensive parallel testing of high-density, MOS random-access memories (RAMs). Parallel test algorithms for RAMs have been developed on the basis of this design-for-testability approach for a broad class of pattern-sensitive faults. Two algorithms which are significantly more efficient than previous approaches are examined. The first algorithm d... View full abstract»

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  • Speedup versus efficiency in parallel systems

    Publication Year: 1989, Page(s):408 - 423
    Cited by:  Papers (164)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1360 KB)

    The tradeoff between speedup and efficiency that is inherent to a software system is investigated. The extent to which this tradeoff is determined by the average parallelism of the software system, as contrasted with other, more detailed, characterizations, is shown. The extent to which both speedup and efficiency can simultaneously be poor is bound: it is shown that for any software system and an... View full abstract»

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  • Fast parallel algorithms for binary multiplication and their implementation on systolic architectures

    Publication Year: 1989, Page(s):424 - 431
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    Two algorithms for parallel multiplication of two n-bit binary numbers are presented. Both use column compression to increase the speed of execution. They require almost regular interconnection between only two types of cells and hence are very suitable for VLSI implementation. Both of them can also be easily modified to handle two's complement numbers with constant differences in time View full abstract»

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  • Mean value analysis by chain of product form queueing networks

    Publication Year: 1989, Page(s):432 - 442
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (812 KB)

    A computational algorithm is developed for closed multichain product-form queueing networks. For networks that consist of only single-server fixed rate and infinite-server service centers, it involves only mean performance measures. The algorithm, called mean value analysis by chain (MVAC), is based on a recursion that is quite different in form from the recursion used in the well-known mean value... View full abstract»

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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org