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Computers and Digital Techniques, IEE Proceedings -

Issue 2 • Date Mar 1995

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Displaying Results 1 - 12 of 12
  • Performance of a neural binary pattern classifier

    Publication Year: 1995 , Page(s): 152 - 156
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (316 KB)  

    The paper describes a binary neural network architecture and its performance in pattern classification. The network is called binary because its inputs are binary and its main components are composed of binary neurons. Apart from the usual input and output layers, the network has two `hidden' layers, called code layer and linear plane, connected in a feedforward structure. The weights of these fee... View full abstract»

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  • Efficient parallel algorithms on optically interconnected arrays of processors

    Publication Year: 1995 , Page(s): 87 - 92
    Cited by:  Papers (10)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (524 KB)  

    Arrays of processors with pipelined optical buses are introduced for the efficient implementation of computationally intensive applications. Techniques for the concurrent transmission of messages over the optical bus to avoid collision of messages is shown. Convenient parallel data movement operations are derived for this architecture, which are then used in the design of parallel algorithms for t... View full abstract»

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  • Design and VLSI implementation of an address generation coprocessor

    Publication Year: 1995 , Page(s): 145 - 151
    Cited by:  Papers (2)  |  Patents (2)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (368 KB)  

    Most applications of general purpose VLSI processors are developed using high level languages. In these languages, information is generally handled in a structured form. Compilers generate a considerable amount of code to navigate through the data structures and considerable processing time is spent performing address calculations required to access the data structures. An alternative to software ... View full abstract»

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  • Fast algorithms for LUC digital signature computation

    Publication Year: 1995 , Page(s): 165 - 169
    Cited by:  Papers (11)  |  Patents (1)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (312 KB)  

    Recently, a digital signature scheme based on a special type of Lucas function has been proposed which is free from the multiplicative attack on the RSA digital signature (P. Smith and M. Lennon, 1993). A disadvantage of this new digital signature scheme LUC is that it takes more computation than the RSA does. An important property, V(x+y)=V(x)×V(y)-V(x-y), of this special type of Lucas func... View full abstract»

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  • Routing and performance of the double tree (DOT) network

    Publication Year: 1995 , Page(s): 93 - 97
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (328 KB)  

    The paper deals with the analysis of an irregular multistage interconnection network called the double tree (DOT) network. A dynamic shortest path routing algorithm for the packet switching DOT network is proposed. The DOT network, being an irregular network, can provide biased pairwise service to favoured connections. Its performance under varying degrees of localised communication is analysed. A... View full abstract»

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  • Genetic algorithm for mapping tasks onto a reconfigurable parallel processor

    Publication Year: 1995 , Page(s): 81 - 86
    Cited by:  Papers (8)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (464 KB)  

    The authors describe a genetic algorithm for a difficult optimisation problem which arises in the context of parallel processing. The problem is to assign each task in the given task graph T to a processor, so as to minimise the total overall execution time of the tasks. Total execution time is computed with the knowledge of individual run times of tasks and the communication requirements among ta... View full abstract»

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  • Efficient global strategy for designing and testing scanned sequential circuits

    Publication Year: 1995 , Page(s): 170 - 176
    Cited by:  Patents (4)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (572 KB)  

    Scan design has been widely used for alleviating the burden of test generation. How to reduce the extra costs caused by the scan design becomes a major target. Previous approaches have tried individually to enhance the abilities of test generation algorithm and scan cell selection strategy. In contrast, a global strategy taking care of the close relationship between these factors and combining a n... View full abstract»

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  • Orientation assignment of standard cells using a fuzzy mathematical transformation

    Publication Year: 1995 , Page(s): 157 - 164
    Cited by:  Papers (2)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (508 KB)  

    It is well known that minimising total wire length reduces routing area in a standard cell layout. After the placement phase, another advanced improvement on total wire length is made by assigning the orientations of standard cells. The authors develop two way constrained fuzzy graph clustering based on fuzzy c-means clustering and the transformation between the orientation assignment of standard ... View full abstract»

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  • Fine grain scheduler for shared-memory multiprocessor systems

    Publication Year: 1995 , Page(s): 98 - 106
    Cited by:  Papers (1)  |  Patents (3)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (564 KB)  

    The Tatung fine grain scheduler (TFGS), which works on machine instruction level for multiprocessor systems, is described. The object of TFGS is to minimise the total execution time of an application program that is to be executed on a shared memory multiprocessor system. An application program is compiled to generate intermediate code. This code is then represented by a data/control dependence gr... View full abstract»

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  • Intelligent code migration technique for synchronisation operations on a multiprocessor

    Publication Year: 1995 , Page(s): 107 - 116
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (644 KB)  

    A compiler technique for migrating synchronisation operations is proposed. The traditional code motion technique is only used for migrating loop invariant statements before the loop; it cannot migrate those synchronisation operations inside the loop. On the other hand, all current statement level synchronisation schemes cannot handle the code migration. However, the performance enhancement is sign... View full abstract»

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  • Cost-performance analysis of cascaded crossbar interconnected multiprocessors

    Publication Year: 1995 , Page(s): 117 - 134
    Cited by:  Patents (1)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (908 KB)  

    The cost performance ratio of interconnection networks for multiprocessors depends upon the connectivity of the network: the processing efficiency of these systems increases when the number of links and switches also increases. The authors study the performance of a class of interconnection networks in which processors and memory modules are grouped into stages, each consisting of a crossbar netwo... View full abstract»

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  • Manifestations of faults in single- and double-BJT BiCMOS logic gates

    Publication Year: 1995 , Page(s): 135 - 144
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (628 KB)  

    Combining the inherent advantages of bipolar and CMOS, BiCMOS is emerging as a major technology for high speed, high performance, digital and mixed signal applications. Logic behaviour of single- and double-BJT BiCMOS devices under transistor level shorts and opens is examined. In addition to sequential behaviour, some stuck open faults exhibit increased delay. While most stuck on faults can be de... View full abstract»

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