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IEEE Transactions on Computers

Issue 3 • Date Mar 1995

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Displaying Results 1 - 13 of 13
  • Computing reliability intervals for k-resilient protocols

    Publication Year: 1995, Page(s):462 - 466
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    k-resilient protocols are used in some parallel and distributed system applications for increased availability of resources. A protocol running on an n site system is k resilient if it could tolerate up to k failures and operate correctly. The reliability of such a protocol is defined as the probability that no more than k sites have failed. Such a k-resilient protocol is beneficial only when its ... View full abstract»

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  • Practical delay enforced multistream (DEMUS) control of deeply pipelined processors

    Publication Year: 1995, Page(s):458 - 462
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    The simulated performance of a practical multithreaded mechanism for achieving high utilization of deeply pipelined (>5 stage) processors is presented. Threads are dynamically interleaved in one pipeline. After each instruction is dispatched, enough delay is introduced so that successive instructions cannot interfere. Four scheduling algorithms, three of which are realizable, are tested on a si... View full abstract»

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  • Fast evaluation of the elementary functions in single precision

    Publication Year: 1995, Page(s):453 - 457
    Cited by:  Papers (39)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    In this paper we introduce a new method for the fast evaluation of the elementary functions in single precision based on the evaluation of truncated Taylor series using a difference method. We assume the availability of large and fast (at least for read purposes) memory. We call this method the ATA (Add-Table lookup-Add) method. As the name implies, the hardware required for the method are adders ... View full abstract»

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  • A fast VLSI-efficient self-routing permutation network

    Publication Year: 1995, Page(s):448 - 453
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    A multistage self-routing permutation network is presented. This network is constructed from concentrators and digit-controlled 2×4 switches. A destination-tag routing scheme is used to realize any arbitrary permutation. The network has O(log2 N) gate-delay and uses O(N2) VLSI-area, where N is the number of inputs. Assuming packet-switching is used for message transmiss... View full abstract»

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  • Test generation for path delay faults using binary decision diagrams

    Publication Year: 1995, Page(s):434 - 447
    Cited by:  Papers (45)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1092 KB)

    A new test generation technique for path delay faults in circuits employing scan/hold type flip-flops is presented. Reduced ordered binary decision diagrams (ROBDDs) are used to represent Boolean functions realized by all signals in the circuit, as well as to represent the constraints to be satisfied by the delay fault test. Two faults are considered for each path in the circuit. For each fault, a... View full abstract»

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  • Parametric dispatching of hard real-time tasks

    Publication Year: 1995, Page(s):471 - 479
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    In many real-time systems relative timing constraints are imposed on a set of tasks. Generating a correct ordering for the tasks and deriving their proper start-time assignments is an NP-hard problem; it subsumes the non-preemptive scheduling problem. Even when the application imposes a total order on the tasks, generating proper start-times is still nontrivial if execution times may range between... View full abstract»

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  • CA-based byte error-correcting code

    Publication Year: 1995, Page(s):371 - 382
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (952 KB)

    This paper reports a novel approach for designing byte error-correcting codes using cellular automata (CA). A simple scheme for generation and decoding of single-byte error-correcting and double-byte error-detecting codes, referred to as CA-SbEC-DbED, is presented. Extension of the scheme to locate/correct larger number of information byte errors has been also included. The encoding and decoding a... View full abstract»

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  • Analytic modeling and comparisons of striping strategies for replicated disk arrays

    Publication Year: 1995, Page(s):419 - 433
    Cited by:  Papers (19)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1320 KB)

    Data replication has been widely used as a means of increasing the data availability for critical applications in the event of disk failure. There are different ways of organizing the two copies of the data across a disk array. This paper compares strategies for striping data of the two copies in the context of database applications. By keeping both copies active, we explore strategies that can ta... View full abstract»

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  • Algorithms for scheduling imprecise computations with timing constraints to minimize maximum error

    Publication Year: 1995, Page(s):466 - 471
    Cited by:  Papers (32)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB)

    We consider the problem of scheduling tasks in the imprecise computation model to minimize the maximum error. Given a task system and a schedule of it, the maximum error of the task system is equal to the error of the task that has the largest error when the task system is executed according to the schedule. We describe two preemptive algorithms for scheduling on a processor n dependent tasks with... View full abstract»

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  • The importance of prepass code scheduling for superscalar and superpipelined processors

    Publication Year: 1995, Page(s):353 - 370
    Cited by:  Papers (15)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1744 KB)

    Superscalar and superpipelined processors utilize parallelism to achieve peak performance that can be several times higher than that of conventional scalar processors. In order for this potential to be translated into the speedup of real program, the compiler must be able to schedule instructions so that the parallel hardware is effectively utilized. Previous work has shown that prepass code sched... View full abstract»

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  • Fault detection in multiprocessor systems and array processors

    Publication Year: 1995, Page(s):383 - 393
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (772 KB)

    Off-line testing of large multiprocessor networks or VLSI chips with many outputs requires a large volume of memory for reference data storage. Space compaction combined with time compression of test responses can essentially reduce an overhead required for testing and diagnosis. In this paper, we discuss the problem of optimal design for space compressors (compactors), to minimize the number of o... View full abstract»

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  • Management of partially safe buffers

    Publication Year: 1995, Page(s):394 - 407
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1144 KB)

    Safe RAM is RAM which has been made as reliable as a disk. We consider the problem of buffer management in partially safe buffers, i.e., buffers which contain both safe RAM and volatile RAM. Buffer management techniques for partially safe buffers explicitly consider the safety of memory in deciding which data to place in the buffer, where to place it, and when to copy updates back to the disk. We ... View full abstract»

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  • A fault tolerant hybrid memory structure and memory management algorithms

    Publication Year: 1995, Page(s):408 - 418
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (880 KB)

    This paper proposes a cost effective fault tolerant memory structure. It uses the modified status of virtual memory pages as the basis to propose a system with two classes of memory. One class is for modified pages, and the other is for pages not modified. The term hybrid memory system is used to describe this system. Results show the cost savings for a hybrid system over a traditional fault toler... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org