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Components, Packaging, and Manufacturing Technology, Part A, IEEE Transactions on

Issue 1 • Date Mar 1995

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Displaying Results 1 - 25 of 31
  • Thin-film decoupling capacitors for multichip modules

    Publication Year: 1995 , Page(s): 174 - 179
    Cited by:  Papers (6)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (568 KB)  

    Thin-film decoupling capacitors based on ferroelectric lead lanthanum zirconate titanate (PLZT) films are being developed for use in advanced packages, such as multichip modules. These thin-film decoupling capacitors are intended to replace multilayer ceramic capacitors for certain applications, since they can be more fully integrated into the packaging architecture. The increased integration that can be achieved should lead to decreased package volume and improved highspeed performance, due to a decrease in interconnect inductance. PLZT films are fabricated by spin coating using metal carboxylate/alkoxide solutions. These films exhibit very high dielectric constants (ε⩾900), low dielectric losses (tan δ≈0.01), excellent insulation resistances (ρ>1013 Ω-cm at 125°C), and good breakdown field strengths (EB≈900 kV/cm). For integrated circuit applications, the PLZT dielectric is less than 1 μm thick, which results in a large capacitance/area (8-9 nF/mm 2). The thin-film geometry and processing conditions also make these capacitors suitable for direct incorporation onto integrated circuits and for packages that require embedded components View full abstract»

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  • Analysis of TAB inner lead fatigue in thermal cycle environments

    Publication Year: 1995 , Page(s): 101 - 107
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (616 KB)  

    The inner leads of a Tape Automated Bonding (TAB) device can be subject to early fatigue failures in thermal cycle environments. This paper describes a 3-D nonlinear finite clement analysis of the failure mechanism, and verifies the results by experiment. Some TAB applications require environmental qualification and electrical testing in the unexcised tape carrier or retain a significant portion of the polyimide tape in the assembly. In these cases the Coefficient of Thermal Expansion (CTE) mismatch between the silicon die and polyimide tape can cause plastic strains in the inner leads. Several design variations are quantified. Those with first order effects were found to be encapsulant material, lead length, and lead material View full abstract»

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  • Liquid cooling performance for a 3-D multichip module and miniature heat sink

    Publication Year: 1995 , Page(s): 68 - 73
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (472 KB)  

    Measured thermal performance is presented for a single phase liquid-cooled module. Tape automated bonded (TAB) thermal test chips and their associated substrates are stacked in a compact, 3-D liquid-tight module. A dielectric liquid, polyalphaolefin (PAO), is forced to flow past the active and inactive sides of TAB chips. At a volumetric flowrate of 0.05 gallons per minute (gpm) and an estimated pressure loss less than 0.5 psi, the measured junction-to-liquid thermal resistance is 2.0 C/W for a 0.50 in.×0.50 in.×0.015 in. thermal test chip. The thermal resistance was also measured for an indirect liquid-cooling approach. PAO was used to cool a miniature sink mounted directly to a 0.50 in.×0.50 in. heat source. The heat source was used to simulate the thermal characteristics of a chip carrier package. The overall dimension of the liquid heat sink is 1.0 in.×1.0 in.×0.28 in. The measured junction-to-liquid thermal resistance is 0.52 C/W for a flowrate of 0.05 gpm, and for an estimated pressure loss less than 1.0 psi. Numerical computational techniques yielded results which were comparable to the measured thermal resistances for both the 3-D module and the miniature heat sink. Enhanced thermal performance gained by introducing micro-encapsulated phase change material (microPCM) to the PAO is estimated for both the 3-D module and the miniature heat sink View full abstract»

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  • Simulations and measurements of picosecond signal transients, propagation, and crosstalk on lossy VLSI interconnect

    Publication Year: 1995 , Page(s): 215 - 225
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (828 KB)  

    Signal transients, propagation, and crosstalk simulations of coupled interconnect lines have been performed, and the results verified by time-domain measurements. These simulations include frequency dependent interconnect circuit parameters, arbitrary loads, and 30 ps rise times. A generalized interconnect transfer function is used to calculate circuit responses in the frequency domain. Then an inverse Fourier transform is employed to predict the time-domain signals. Frequency variant TC interconnect models and PISCES-II simulations are used to determine the interconnect circuit model parameters. The simulation results are compared with conventional interconnect circuit models such as LC, RC, and RLC networks. Time-domain interconnect measurements using a HP54121T sampling oscilloscope show excellent agreement with simulations. Thus, signal transients, propagation, and coupling noise of on-chip interconnects are predicted View full abstract»

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  • Radio-frequency connector and interconnect reliability in spaceborne applications

    Publication Year: 1995 , Page(s): 163 - 169
    Cited by:  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (620 KB)  

    In addition to quality electronic components and subsystems, highly reliable interconnects are imperative in high-reliability applications such as spacecraft and satellites. System designers must therefore address and resolve issues related to the proper design and assembly process for connectors and interconnects for passive and active components. We have developed guidelines for the design of a space-qualifiable connector system based on our experience with defective hybrid couplers and power dividers, as well as our understanding of the material properties of the connector dielectric. We also discuss testing and the qualification of vendors of connectors and interconnects necessary to ensure high-reliability radio frequency and microwave components View full abstract»

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  • Capacitance monitoring while flex testing

    Publication Year: 1995 , Page(s): 180 - 186
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (624 KB)  

    As most other modes of failure for surface mount ceramic capacitors have been dramatically reduced over the years, cracking due to stresses from board bending have gained prominence. Cracking in ceramic capacitors can lead to instant failures or insidious, future field failures. The crack allows current leakage through the dielectric insulator with a voltage applied. This voltage can be much less than the rated voltage of the capacitor and still result in excessive leakage. Early attempts to identify susceptibility to this type of failure and the refinement of these techniques to establish a reliable and repeatable test with variables type of ratings is detailed within View full abstract»

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  • Carrier and socket technology for high pin count QFP packages

    Publication Year: 1995 , Page(s): 136 - 141
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (396 KB)  

    The carrier and socket technology for high pin count Quad Flat Pack (QFP) packages is a set of three components that can be used in various combinations, that allow for easier manipulation of fine pitch, (fine pitch defined as packages having a lead tip to lead tip spacing of 0.65 millimeters or less), QFP between various shipping, test, programming, and prototype environments. The three components are the small outline carrier, surface mountable development socket, and through hole mountable programming socket. The carrier is designed to protect the leads of the QFP from deformation, while allowing the leads to make electrical connection with the contacts of the two different sockets. The development socket is surface mountable with a footprint that is identical to the naked QFP housed within the carrier. The programming socket is a through hole mountable, clam-shell socket, which accepts the same carrier as the development socket. The carrier and socket technology was developed primarily to assist in the development and prototyping of re-configurable QFP devices. Specifically, those QFP devices that need to be placed in a different electrical environment to be re-configured, than the electrical environment the device will be in, once it has been configured to the users satisfaction View full abstract»

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  • Intrinsic thermocouple monitor for laser wirebonding

    Publication Year: 1995 , Page(s): 206 - 214
    Cited by:  Papers (2)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (496 KB)  

    The use of the thermoelectric voltage generated between the tip and the wire during laser wirebonding is described as a process monitor. The change in thermoelectric response during melting of the wire is detected and used to control the laser pulselength. Thus, optimum bonding is achieved independent of thermal environment at different pad locations. The use of the process monitor for bonding on gold pads on multilayer alumina substrates is described in detail View full abstract»

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  • Influence of temperature and humidity on the wettability of immersion tin coated printed wiring boards

    Publication Year: 1995 , Page(s): 153 - 162
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (816 KB)  

    Immersion tin films applied in various thicknesses (0.2-2 μm) to different copper substrates were characterized relative to thermal stability and shelf life. Thermal excursions included those typical in mixed technology assembly processes. Exposure to temperature/humidity was varied from near ambient (35°C/85% RH) to harsh (steam aging). A minimum thickness of ~60 μin (1.5 μm) was determined to be critical for assembly operations involving multiple thermal excursions. Even though formation of CuSn intermetallic compounds (IMC) is facile, at the copper-tin interface, these compounds do not adversely affect the soldering performance, as long as the IMC phase is protected by a tin surface layer. Immersion tin finishes are relatively stable to thermal exposure, but are readily oxidized in the presence of humidity. This oxide growth is directly responsible for solderability degradation. The underlying copper substrate was also found to have a significant impact on the thermal stability of tin films. An electroless copper substrate caused significantly more intermetallic formation, which resulted in poor solderability even under moderate temperature/humidity conditions View full abstract»

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  • Manufacturing stresses in the die due to the die-attach process

    Publication Year: 1995 , Page(s): 201 - 205
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (396 KB)  

    During the die-attach process, residual stresses are developed in components of the die-attach assembly due to the mismatch of coefficients of thermal expansion of different materials. To properly assess the service life of the assembly, those stresses must be taken into account. Several test dies, with and without chip's protective coating, were prepared, and two different bonding materials, “low-stress” and “high-stress”, were used for analysis of the die-attachment induced stresses. An experimental technique, the digital image analysis enhanced moire interferometry (DIAEMI), was utilized to observe the initial and final (after die-attach) surface contour patterns of dies. This information was used to obtain the in-situ out-of-plane displacements of the die due to the die-attach process, and the induced stresses were calculated by a hybrid finite element method. The results show that stresses in die induced by high-stress bonding materials are on average five times higher than the stresses induced by low-stress materials; during the process some of the residual stresses induced by the chip's coating were released. By comparing the results with the straightforward finite element method prediction, it is shown that the induced stresses are much lower than those stresses predicted by the straightforward finite element calculation View full abstract»

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  • Fine line circuit manufacturing technology with electroless copper plating

    Publication Year: 1995 , Page(s): 127 - 135
    Cited by:  Papers (5)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (972 KB)  

    Two types of additive processes for fine circuit pattern manufacturing technology using electroless copper plating have been developed. The processes offer high dimensional accuracy. Technical aspects of the additive processes, materials for the fabrication of additive circuits, and the performance of these circuits are reported here View full abstract»

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  • Reliability development and qualification of a low-cost PQFP-based MCM

    Publication Year: 1995 , Page(s): 10 - 14
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (476 KB)  

    In Motorola's experience with commercial MCM customers, cost and size reduction are the largest driving factors for interest in MCM's. Speed and other performance factors are of secondary interest. Development and qualification can add significantly to the total cost of an MCM, so in addition to the normal desire to provide reliable products, the cost of doing so has gained increased importance. Motorola has identified three key factors in providing cost-effective MCM's: leverage single chip package experience, qualify MCM product families (package types), and use only qualified silicon devices in MCM products. This paper describes application of the three key factors to the reliability qualification of the 28-mm MCML Series package, a PQFP-(Plastic Quad Flat Pack) based MCM. An initial reliability evaluation was performed to investigate reliability issues. As a result of the initial evaluation, changes were made to assembly processes and materials. The MCM was then submitted to a suite of reliability stresses selected to evaluate mechanical, thermo-mechanical, moisture, and longevity performance. The MCM passed electrical and visual (SAT, or Scanning Acoustic Tomography) reliability requirements for all stresses, and performed well in extended stress tests as well. A procedure is in place to help insure high reliability for additional products in the 28-mm PQFP-based MCM package View full abstract»

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  • Silicon on insulator-an emerging high-leverage technology

    Publication Year: 1995 , Page(s): 187 - 194
    Cited by:  Papers (2)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (704 KB)  

    Silicon on insulator (SOI) has emerged as a high-leverage technology for a wide range of commercial and military applications. While the use of SOI is presently limited to special niche applications, such as radiation-hard space and defense electronics, thin-film SOI has become strategic for low-power, battery-operated portable systems and large-scale integrated logic and memory circuits with sub-half micron features. Substantial process simplification and cost reduction result from the dielectrically isolated structures. Other important SOI applications are the merger of several functions on the same die that performs reliably in adverse high-temperature environments. These include analog and logic functions, smart micromechanical sensors for automotive and distributed jet engine control with logic functions, or smart high-voltage CMOS logic/control elements. Manufacturable solutions to several material and device problems, however, must be demonstrated before SOI CMOS or BiCMOS designs enter the high-volume commercial manufacturing stage. Among these are the availability, cost, and quality of SOI material, gettering, electrostatic discharge protection, the floating-body problem in thin-film structures, and self-heating effects caused by the low thermal conductivity of the buried-oxide layer. The status of SOI material is discussed, including the different methods used to prepare large SOI wafers, wafer availability, cost reduction strategies, material characterization, and material quality. Applications and leverage areas are also described, with emphasis on problems and challenges that lie ahead for the large-scale manufacture of SOI products. The potential economic impact of SOI technology on the profitability of semiconductor manufacturing is described View full abstract»

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  • Gold wire weakening in the thermosonic bonding of the first bond

    Publication Year: 1995 , Page(s): 230 - 234
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (356 KB)  

    Factors that are likely to weaken gold wire during thermosonic wirebonding of the first bond on the die pad are studied. The studies show that weakening is due mainly to the golf club ball formation, grain growth of wire, neckdown formation, tie-bar severance, and the wire-scratching phenomenon. Golf club ball formation can be eliminated by long tail length and wire grain size after recrystallization, can be reduced by low current supplied and short spark time during the EFO excitation. Neckdown and tie-bar severance can be removed by introducing reverse loop and ensuring no indexing problem during the wirebonding process. Wire scratching and dragging due to inside chamfer can be eliminated when the capillary for bonding is not too worn out View full abstract»

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  • High reliability internal capacitor of LTCC

    Publication Year: 1995 , Page(s): 170 - 173
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB)  

    The authors discuss the internal capacitor of a low-temperature ceramic circuit (LTCC). They include the material study, manufacturing process, electronic properties, and reliability of the internal capacitor. After this study, a highly reliable internal capacitor is developed and this result makes this technology closer to real application View full abstract»

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  • Exceptional performance from the development, qualification and implementation of a silicone adhesive for bonding heatsinks to semiconductor packages

    Publication Year: 1995 , Page(s): 94 - 100
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (624 KB)  

    The stress induced by the Coefficient of Thermal Expansion (CTE) mismatch of ceramic semiconductor packages bonded to aluminum heatsinks created a high risk of cracking. As packages increase in size and power, the need for an advanced adhesive with compliant properties, reliable bond strengths and high thermal performance is required. The demand for high speed semiconductor CPU's in today's marketplace created a requirement for an effective, low-cost thermal management solution for packaging. This paper describes the methodology and analysis used to develop, qualify, and implement a new heatsink adhesive attach strategy into manufacturing. Included are the resultant benefits and potential applications for future product designs using this Low Modulus Adhesive (LMA). The project goal was to “Implement LMA into manufacturing for all permanent heatsink attach products”. This included both current and future products, with the heatsink attach strategy of “low volume, high mix” product capability. As a result of the work reported here, heatsink attach capabilities have been enhanced significantly with attractive cost benefits. Concurrent engineering was emphasized to deliver a high quality and low-cost process to production in a timely manner. The material, process, and equipment has been running in a low volume production facility with 100% yield. This technology is planned for transfer to a high volume production facility View full abstract»

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  • Thermal enhancement of plastic IC packages

    Publication Year: 1995 , Page(s): 57 - 67
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (996 KB)  

    Plastic package thermal enhancement techniques that improve the heat dissipating capabilities of the packages are available to IC package design engineers. Evaluations of these techniques have been performed using test structure measurements and thermal FEA modeling. The techniques studied include the use of additional metal traces on the PCB to spread the heat away from the package, the use of heat slugs and heat spreaders inside the package to enhance heat transfer to the package leads and package body, and the use of high thermal conductivity mold compounds to improve thermal performance. Package types ranged from 8 pin SOIC's to 208 PQFP's with a broad range of chip sizes. Details of the measurement and modeling techniques are given with comparison of the models to the experimental results in many instances View full abstract»

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  • Environmental stress testing experiment using the Taguchi method

    Publication Year: 1995 , Page(s): 3 - 9
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (492 KB)  

    Manufacturing process improvements which increase productivity, decrease test process time, and improve customer satisfaction are highly desirable in today's marketplace. The application of environmental stress screening (ESS) is a method of achieving these improvements. ESS is the application of stresses applied beyond product specification limits in order to find latent product defects. Utilizing ESS achieves increased robustness and lower infant mortality. An experiment was performed to identify the significance or relevancy of the selected stresses for application in the printed wiring board (PWA) production process by using a statistically significant controlled method. The design of experiments statistical approach (analysis of variance), is applied, combined with the Taguchi two-level, seven-factor design method. This experiment concentrated on three stresses (temperature cycling, random vibration, and power cycling) and two diagnostic levels: a prom-based (programmable memory chip), power-on self test (POST), and a functional diagnostic test suite, contained on disk storage. Note that this was not an optimization experiment. Once the significance to the production process is identified, future optimizing of temperature cycling, power cycling, and vibration screens, will be conducted. Also, voltage margining was not included so as to reduce the complexity of the experiment-treatment factors and interactions. Experimental results and conclusions on the effectiveness of different stress regimens are presented in this paper View full abstract»

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  • A boundary element formulation of the conjugate heat transfer from a convectively cooled discrete heat source mounted on a conductive substrate

    Publication Year: 1995 , Page(s): 108 - 116
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (628 KB)  

    A novel formulation is presented for solving the conjugate heat transfer problem that arises due to a thin flush heat source mounted on a conductive substrate. The geometry is a paradigm for direct air cooling of components on conducting boards. PCB thermal algorithms based on this approach are being developed for rapid estimation of the thermal field in a direct air-cooled board. The algorithms are part of a suite of tools for integrated electronic packaging design being developed at the Center for Electronic Packaging Research (CEPR). This paper presents the formulation of the approach and demonstrates its utilization for parametric studies of board level thermal management, in particular for studying the effects of board conductivity. The unique formulation allows one to couple a wide variety of flow models to the solid conduction. The solid side is modeled with a Boundary Element Method (BEM). The temperature field in the fluid side is not explicitly solved, rather, analytical “step temperature” solutions, relevant to the particular flow model, are used to express convective heat flux as a function of interface temperatures. A noniterative solution for the conjugate problem is found by matching the temperatures and fluxes at the solid-fluid interface. Results of a parametric study of the effects of board conduction on component thermal performance are presented View full abstract»

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  • Process considerations in the fabrication of fluoropolymer printed circuit boards

    Publication Year: 1995 , Page(s): 118 - 126
    Cited by:  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (996 KB)  

    Fluoropolymer-based dielectric materials provide desirable electrical and mechanical properties when used as insulator materials for printed wiring boards (PWBs). However, along with the significant performance and reliability advantages of these insulator materials for microwave and high speed digital applications, there are also significant processing challenges. This paper reviews the significant electrical and mechanical properties of fluoropolymer-based packaging materials, and discusses the unique processing challenges encountered in the fabrication of PTFE printed circuit boards and modules. Key features of the TSM Microelectronics High Performance Carrier fabrication process will be described as they relate to those challenges View full abstract»

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  • Thermal characterization of a Tape Carrier Package

    Publication Year: 1995 , Page(s): 75 - 81
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (520 KB)  

    The unenhanced thermal performance of 20 mm Tape Carrier Packages (TCP) packages on 8 layer boards with internal planes is 19°C/W. Package thermal resistance Θjc has been measured at 2°C/W. Simple PCB enhancements such as the addition of thermal vias, alone or with the use of low profile heat sinks, brings the thermal performance in line with requirements for mobile computing platforms which do not have forced convection cooling options available. With forced convection cooling, devices with power dissipation requirement of 5°C/W and higher can be packaged in TCP format View full abstract»

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  • An investigation of solder joint fatigue using electrical resistance spectroscopy

    Publication Year: 1995 , Page(s): 142 - 152
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1072 KB)  

    Interconnect electrical resistance is examined as a possible bases for a reliability tool. Measurements are reported of the resistance change of lap shear (60% Sn-40% Pb) solder joints as a function of fatigue. The expected dependence of electrical resistance on elastic strain, plastic deformation, and cyclic fatigue is reviewed. An analytical framework is developed to examine the observed electrical resistance change. A technique called resistance spectroscopy was used to measure the small resistance change resulting from the strain and fatigue in the presence of much larger resistance changes resulting from temperature and other fluctuations. The level of the noise in the resistance measuring system used for the lap shear joints was less than one nano-ohm. The lap shear solder joints exhibited a systematic resistance change as the specimens were cycled toward failure. Initially the average resistance increased, followed by a much stronger decrease, and lastly increased markedly as crack propagation began. The decreasing-resistance portion of this signature occurs prior to crack initiation, and can be used to detect incipient solder joint failure more quickly and with greater ease than present techniques View full abstract»

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  • Analysis of thermal transient data with synthesized dynamic models for semiconductor devices

    Publication Year: 1995 , Page(s): 39 - 47
    Cited by:  Papers (40)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (676 KB)  

    A technique for synthesizing dynamic models comprised of discrete thermal resistances and capacitances directly from thermal step-response data on packaged semiconductor devices has been developed. Such models reveal the effective internal-package thermal resistances which comprise the overall junction-to-ambient or junction-to-case thermal resistance. These models can discriminate lumped internal constituent resistances including die/die-attachment spreading, internal package spreading, and case-to-air dissipation. The thermal step-response has been experimentally and analytically studied using the electrical method of junction temperature measurement. The interpretation and accuracy of these synthetic models have been investigated on a collection of test-case devices. Overshoot anomalies exhibited by junction-to-case thermal step responses have been examined experimentally and explained with synthetic model analysis. The application of synthetic models to computing thermal impedance for nonconstant or cyclic device-powering conditions is also presented View full abstract»

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  • An exact recursion relation solution for the steady-state surface temperature of a general multilayer structure

    Publication Year: 1995 , Page(s): 31 - 38
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (652 KB)  

    A recursion relation technique has been used in the past to determine the surface potential from the multilayer electrical Laplace equation. This has provided for a vastly simplified evaluation of the electrical spreading resistance and four-probe resistance. The isomorphism of the multilayer Laplace equation and the multilayer steady-state heat flow equation suggests the possibility of developing a recursion relation applicable to the multilayer thermal problem. This recursive technique is developed and is shown to provide the surface temperature of the multilayer steady-state heat flow equation. For the three-layer case, the thermal recursion relation readily yields the surface results,which are identical with those presented by Kokkas and the TXYZ thermal code. This recursive technique can be used with any number of layers while incurring only a small increase in computation time for each added layer. For the case of complete, uniform top surface coverage by a heat source, the technique gives rise to the generalized one-dimensional thermal resistance result. An example of the use of the new recursive method is provided by the preliminary calculations of the surface temperature of a buried oxide (SOI, SIMOX) structure containing several thicknesses of the surface silicon layers. This new technique should prove useful in the investigation and understanding of the steady-state thermal response of modern multilayer microelectronic structures View full abstract»

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  • An effective alternative for marginal thermal improvements of semiconductor devices

    Publication Year: 1995 , Page(s): 48 - 56
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (864 KB)  

    The traditional approaches to improving device thermal performance include expensive redesign of the package housing the chip and/or the expensive modification of the thermal environment surrounding the packaged chip. This paper reports the results of using various different methods for improving semiconductor thermal performance of specific surface mount packages. Data is presented for several different thermal environment conditions and package variations. The environmental conditions include still-air, moving-air, heat sink, and tape sink. The package variations studied include die attachment thickness, internal heat spreader, and encapsulant material variations. The tape heat sink, consisting of embossed copper foil with high thermal conductivity adhesive on one side, was applied to the top surface of the test samples. The resultant thermal resistance was improved by 15%-20%, depending on the specific package version and, in some cases, was approximately equivalent in thermal terms to a 500 lfpm (linear feet per min) moving-air environment. The data results indicate that significant marginal thermal performance improvements can be realized with a relatively low-cost tape heat sink approach. The methodology for the thermal measurements is described in sufficient detail so that further data can be taken and compared for alternative packages and/or thermal environment improvements View full abstract»

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Aims & Scope

This Transaction ceased production in 1998. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope