IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 2 • Feb 1995

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Displaying Results 1 - 12 of 12
  • Modeling of VLSI RC parasitics based on the network reduction algorithm

    Publication Year: 1995, Page(s):137 - 144
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (708 KB)

    This paper presents a method of modeling of R and C parasitics in VLSI circuits. A network representation is generated for finite difference discretization of 2-D Laplace's equation, and a reduction algorithm is applied to this network. The solution area can be defined by any set of polygons. If n is the number of discretization nodes the new algorithm is O(n1.5). It yields directly the... View full abstract»

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  • Circuit clustering using a stochastic flow injection method

    Publication Year: 1995, Page(s):154 - 162
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (660 KB)

    We present a new clustering metric, based on a random graph model and a ratio cut concept. The minimization of the proposed clustering cost can be transformed to a uniform multicommodity flow problem by adding artificial weight functions, which can be solved by a multicommodity flow-based algorithm with high complexity. We devise a probabilistic flow injection approach which drastically reduces th... View full abstract»

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  • Relaxation-based transient sensitivity computations for MOSFET circuits

    Publication Year: 1995, Page(s):173 - 185
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1028 KB)

    In this paper, we propose two new methods for computing the transient sensitivities of large scale MOSFET circuits, which exploit the relaxation-based circuit simulation techniques, the waveform relaxation (WR) method and the iterated timing analysis (ITA) method. Sufficient conditions are stated and proven, which are quite mild for MOSFET circuits, for convergence of these new methods. A pruning ... View full abstract»

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  • Optimal net assignment

    Publication Year: 1995, Page(s):265 - 269
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    We study in this paper the net assignment problem subject to the capacity constraint, selection constraint and routing constraint. Given two adjacent channels separated by a cell row, and a set of nets in each of the two channels, this problem is to assign to the cell row a subset of nets in each channel such that without violating any given constraint, the sum of the remaining densities of the tw... View full abstract»

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  • Optimization by iterative improvement: an experimental evaluation on two-way partitioning

    Publication Year: 1995, Page(s):145 - 153
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (760 KB)

    Recently, Johnson et al. [1989] presented an excellent comparison of simulated annealing and Kernighan-Lin algorithms. However, their test beds were limited to random and geometric graphs. We present a complete evaluation by adding real circuitry into the test beds. A two-level partitioning algorithm called the primal-dual algorithm is also incorporated for comparison. We show that at least 500 ru... View full abstract»

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  • New RTD large-signal DC model suitable for PSPICE

    Publication Year: 1995, Page(s):167 - 172
    Cited by:  Papers (35)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    A new resonant-tunnel diode (RTD) large-signal DC model suitable for PSPICE simulation is presented in this paper. For better accuracy, the model equations are deliberately chosen through the combination of Gaussian and/or exponential functions, and it can be easily implemented in PSPICE using the FUNCTION statement. Most of the associated parameters required in this new model have explicit relati... View full abstract»

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  • On correction of multiple design errors

    Publication Year: 1995, Page(s):255 - 264
    Cited by:  Papers (37)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1024 KB)

    We consider the problem of correcting multiple design errors in combinational circuits and in finite-state machines. The correction method introduced for combinational circuits uses a single error correction scheme iteratively to correct multiple errors. It uses a heuristic measure that guides the selection of single, local circuit modifications that reduce the distance between the incorrect imple... View full abstract»

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  • Development of a C-continuous small-signal model for a MOS transistor in normal operation

    Publication Year: 1995, Page(s):163 - 166
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    An explicit and single-piece model for MOSFET's has been developed. The expressions for the dc current and total charges are C ∞-continuous through all regions of normal operation. The correctness and the advantages of the new model are checked by comparing with HSPICE simulations. Good agreement with the dc and charge models implemented in HPSPICE has been found. Besides, the sma... View full abstract»

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  • Analog IC design automation. I. Automated circuit generation: new concepts and methods

    Publication Year: 1995, Page(s):218 - 238
    Cited by:  Papers (33)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2100 KB)

    The research presented in this paper is concerned with the automation of analog integrated circuit design and, in particular, with a description of methods and techniques employed by the ISAID design system developed at Imperial College, UK. ISAID is comprised of two modules: the circuit generator and the circuit corrector. The circuit generator is based on newly developed methods that are used to... View full abstract»

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  • Analog IC design automation. II. Automated circuit correction by qualitative reasoning

    Publication Year: 1995, Page(s):239 - 254
    Cited by:  Papers (19)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1344 KB)

    For pt. I see ibid., vol. 14, no. 2, p. 218-38 (1995). This part of the paper is focused on a novel application of Qualitative Reasoning, which allows modifications of a circuit's topology to take place in cases where not all performance specifications are met. Within ISAID, this task of post-simulation circuit correction is carried out by the Circuit Corrector View full abstract»

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  • Timing optimization by gate resizing and critical path identification

    Publication Year: 1995, Page(s):201 - 217
    Cited by:  Papers (8)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1492 KB)

    Due to the rapid progress in VLSI technology, the overall complexity of the chip has increased dramatically. There is a simultaneous need for more functions and higher speed in modern VLSI engineering. Therefore, use of a minimum amount of extra hardware to meet timing requirements is becoming a major issue in VLSI design. Here, we propose an efficient method for timing optimization using gate res... View full abstract»

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  • Analysis of interconnect networks using complex frequency hopping (CFH)

    Publication Year: 1995, Page(s):186 - 200
    Cited by:  Papers (230)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1232 KB)

    With increasing miniaturization and operating speeds, loss of signal integrity due to physical interconnects represents a major performance limiting factor of chip-, board- or system-level design. Moment-matching techniques using Pade approximations have recently been applied to simulating modelled interconnect networks that include lossy coupled transmission lines and nonlinear terminations, givi... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu