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Electron Devices, IEEE Transactions on

Issue 2 • Date Feb 1995

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Displaying Results 1 - 25 of 29
  • A new approach for modeling of current degradation in hot-electron damaged LDD NMOSFETs

    Page(s): 362 - 365
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    An analytical model describing current degradation in hot-electron damaged LDD NMOSFETS is proposed. The basic idea of the model is that the drain current degradation can be explained in terms of an increase in the parasitic resistance only. Good agreement with measured data over at least three decades of stress time is obtained with our model View full abstract»

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  • Frequency-resolved measurements for the characterization of MOSFET parameters at low longitudinal field

    Page(s): 315 - 320
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    A new technique is presented to extract the main parameters required for transistor modeling at low longitudinal fields (parasitic resistance, intrinsic conductivity factor, threshold voltage, and body factor k) from a single MOSFET. The method makes use of easy-to-perform AC frequency-resolved measurements to overcome repeatability and accuracy problems encountered with DC data. The technique has been satisfactorily validated on MOSFET's down to 0.8 μm channel length View full abstract»

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  • Characteristics of self-induced lightly-doped-drain polycrystalline silicon thin film transistors with liquid-phase deposition SiO2 as gate-insulator and passivation-layer

    Page(s): 307 - 314
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (656 KB)  

    As the passivation layer on the top of undoped offset region for offset-gate structured poly-Si TFTs is exposed to hydrogen plasma, a lightly-doped-like drain region could be equivalently self-induced. The hydrogenated polycrystalline silicon thin-film transistor of this structure, named self-induced lightly-doped-drain (SI-LDD) poly-Si TFTs, was first developed with liquid-phase deposition oxide as both the gate insulator and the passivation layer. This paper describes the optimum hydrogenation condition, and the electrical characteristics for the novel SI-LDD poly-Si TFTs. The effects of DC electrical stress on SI-LDD poly-Si TFTs are also described. Finally a model is proposed to explain the degradation phenomena observed in our SI-LDD devices View full abstract»

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  • Measurement of junction temperature of an AlGaAs/GaAs heterojunction bipolar transistor operating at large power densities

    Page(s): 358 - 360
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB)  

    An electrical method to determine the junction temperature of a power bipolar transistor is presented. The success of this method does not rely on the constancy of thermal resistance over the wide range of operating temperatures. It is hence suitable for transistors operating at high power densities where conventional measurement techniques would not apply. Using this method, we establish that the junction temperature can be 40°C higher than the product of the low temperature thermal resistance and the power dissipation View full abstract»

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  • High performance poly-Si TFTs fabricated using pulsed laser annealing and remote plasma CVD with low temperature processing

    Page(s): 251 - 257
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    Key technologies for fabricating polycrystalline silicon thin film transistors (poly-Si TFTs) at a low temperature are discussed. Hydrogenated amorphous silicon films were crystallized by irradiation of a 30 ns-pulsed XeCl excimer laser. Crystalline grains were smaller than 100 nm. The density of localized trap states in poly-Si films was reduced to 4×1016 cm-3 by plasma hydrogenation only for 30 seconds. Remote plasma chemical vapor deposition (CVD) using mesh electrodes realized a good interface of SiO 2/Si with the interface trap density of 2.0×1010 cm-2 eV-1 at 270°C. Poly-Si TFTs were fabricated at 270°C using laser crystallization, plasma hydrogenation and remote plasma CVD. The carrier mobility was 640 cm2/Vs for n-channel TFTs and 400 cm2/Vs for p-channel TFTs. The threshold voltage was 0.8 V for n-channel TFTs and -1.5 V for p-channel TFTs. The leakage current of n-channel poly-Si TFTs was reduced from 2×10-10 A/μm to 3×10-13 A/μm at the gate voltage of -5 V using an offset gate electrode with an offset length of 1 μm View full abstract»

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  • Breakdown analysis of an asymmetrical double recessed power MESFET's

    Page(s): 209 - 214
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    FET's with double stepped gate recess are commonly admitted to be presently a very convenient structure capable to overcome the fundamental power limitation related to the breakdown voltage. The present paper deals with an analysis of a double recessed MESFET with a very good and instructive breakdown performance. For the first time we explain on the basis of gate current observations why the double recess structure allows a large breakdown improvement not only at pinch off voltage but also at open channel. Moreover it is shown that the breakdown optimization is fully compatible with the microwave gain performance View full abstract»

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  • A physically based C-continuous model for small-geometry MOSFET's

    Page(s): 283 - 287
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (348 KB)  

    An explicit single-piece MOSFET model is derived from a surface potential formulation. The model covers small-geometry effects, like mobility reduction, channel-length modulation, carrier velocity saturation, and short- and narrow-channel effects. Good agreement has been found with measured characteristics. Furthermore, the DC current calculated using the new model shows smooth transitions through all regions of operation. Therefore the convergence when employed in circuit simulation will be improved View full abstract»

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  • Beam focusing for field-emission flat-panel displays

    Page(s): 340 - 347
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    A combination of finite element and finite difference techniques have been used to simulate the performance of micro-fabricated gated field emitters for flat-panel display applications. The computer model has been verified against both analytic models and experimental data for unfocused devices and then applied to the study of focused structures for which sufficient models and data are not yet available. Quantitative results include electrode current-voltage characteristics and electron beam widths as a function of distance from the cathode. Practical issues such as visual image quality, electrical stress and fabrication complexity are considered to identify a practical design for use in conjunction with existing high-efficiency cathode ray tube phosphors. It is found that the addition of an integrated aperture electrode to focus the emitted electrons increases the cathode-gate drive voltage by about 30% over the case of unfocused emitters. A concentric electrode design results in only 15% increase and promises simpler fabrication. Both approaches demonstrate electron beam widths of tens of microns at anode distances of several millimeters, allowing for full-color resolution in excess of 100 lines per inch with proven color phosphors View full abstract»

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  • Direct measurement of the carrier leakage out of the active region in InGaAsP/InP laser heterostructures

    Page(s): 215 - 218
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (336 KB)  

    Leakage of electrons out of the active region of InGaAsP/InP laser heterostructures at different temperatures was measured by a purely electrical method. Comparison of the obtained results with the results of modeling indicates that special attention should be paid to the acceptor doping levels in the p cladding layer immediately adjacent the active region. Lower acceptor concentration may lead to unacceptably high thermionic leakage View full abstract»

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  • Characteristics of new dielectric isolation wafers for high voltage power IC's by single-Si poly-Si direct bonding (SPSDB) technique

    Page(s): 356 - 358
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (304 KB)  

    Physical and mechanical characteristics of a new DI (Dielectric Isolation) wafer based on a single-Si poly-Si direct bonding (SPSDB) technique were investigated to reduce wafer warpage, increase wafer size and decrease minimum device patterning size. Developed SPSDB wafers of 5-inch size had unchanging warpage height and high bonding strength. When SPSDB wafers were bonded at 1100°C for 2 h, the latter property was comparable to that of the thermal oxidizing layer interface View full abstract»

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  • A novel MESFET fabricated by a simple internal interconnection technique

    Page(s): 370 - 372
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (236 KB)  

    A new type of internal interconnection of devices has been developed by implanting a buried horizontal n+ layer and vertical n+ columns inside semi-insulating GaAs. Based on this technique, a novel MESFET with small intrinsic gate-source resistance has been fabricated and tested View full abstract»

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  • Cutoff frequency and responsivity limitation of AlInAs/GaInAs MSM PD using a two dimensional bipolar physical model

    Page(s): 231 - 238
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (700 KB)  

    Using a 2-D bipolar physical model we highlight the main parameters that govern the long-wavelength MSM PD performance (cutoff frequency and responsivity). This covers applied potential, electrode spacing, absorbing layer thickness, and heterojunction effect. We also report that using a backside illumination technique and a thin absorbing layer we can reach a cutoff frequency as high as 65 GHz with a responsivity of 0.2 A/W View full abstract»

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  • An improved analytical solution of energy balance equation for short-channel SOI MOSFET's and transverse-field-induced carrier heating

    Page(s): 301 - 306
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (440 KB)  

    This paper presents a method for solving the one-dimensional (1-D) energy balance equation for fully depleted short-channel SOI MOSFET's. This method takes the exact kinetic energy into account and provides a new analytical solution for the non-saturated drain current region. The carrier temperature for spatially homogeneous case is described as a function of the longitudinal electric field and the carrier concentration deviation. The electron temperature is higher than that predicted by old models, which is examined by the two-dimensional simulation. The experimental data on gate current characteristics in short-channel SOI nMOSFET's can be physically interpreted by the proposed 1-D model View full abstract»

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  • An investigation of graded and uniform base GexSi1-x HBT's using a Monte Carlo simulation

    Page(s): 201 - 208
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    A fully self-consistent Monte Carlo simulation has been used to investigate electron transport through the base-collector region of various Gex Si1-x based heterojunction bipolar transistors. By considering a range of Ge content in the base of such devices we have shown that the base transit time decreases significantly as the Ge content of the base is increased from 0% to 15% but remains essentially unchanged by a further increase to 30%. Furthermore, it is shown that high current densities can beneficially affect the field distribution in the collector, substantially reducing the collector transit time. A modified form of the simulation has been used to investigate a graded base heterojunction bipolar transistor, with a maximum Ge content of 30%. By including the variation of effective masses across the base we have been able to show how deviations from linear grading can be modelled and to prove that such configurations can produce improvements for base transit times View full abstract»

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  • Modeling of the collector epilayer of a bipolar transistor in the MEXTRAM model

    Page(s): 274 - 282
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (548 KB)  

    A new model description for the behaviour of epitaxial collectors in bipolar transistors is given. This is part of MEXTRAM, a compact model for circuit simulation, and it gives the voltage drop and stored minority carrier charge in the collector epilayer as a function of the bias conditions. It covers (total) depletion and quasi-saturation for both ohmic and space charge conditions in the end region of the epilayer. New features are that the collector current and stored charge are given as explicit analytical functions, thus guaranteeing continuity also for their derivatives, and that collector current spreading is taken into account View full abstract»

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  • Forward biased safe operating area of emitter switched thyristors

    Page(s): 334 - 339
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    The physical mechanisms for current saturation and destructive failure of the dual channel emitter switched thyristor (EST) are described. Forward Biased Safe Operating Areas (FBSOAs) at short-circuit state of the 600 V and 2500 V dual channel ESTs are reported. It is demonstrated by numerical simulation that the EST offers a better FBSOA than the IGBT. Experimental measurements are reported that corroborate these calculated results View full abstract»

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  • Transconductance enhancement due to back bias for submicron NMOSFET

    Page(s): 288 - 294
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    For the first time, a new phenomenon of transconductance enhancement due to back bias found in submicron MOSFET's is reported. A two-dimensional numerical simulation has been performed to investigate the origin of this observation. The enhancement of the channel potential gradient is verified to be the main reason responsible for this anomalous transconductance enhancement effect. Moderate channel doping concentrations (5×1016~5×1017 cm-3), short channel lengths (submicron regime), and operation under small drain bias are three key conditions for the maximum transconductance enhancement due to the back bias to occur. A conventional linear I-V model, which employs an effective channel length defined by the source/drain metallurgical junctions and bias-independent source/drain extrinsic resistance is not able to predict such characteristics View full abstract»

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  • Linear theory of slow wave cyclotron interaction in double-ridged folded rectangular waveguide

    Page(s): 348 - 355
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    A general dispersion relation for slow wave cyclotron traveling wave interaction in a folded waveguide is derived from a fluid dynamical treatment. The serpentine structure is formed by folding a double-ridged rectangular waveguide so that the orientation of the magnetic field changes (H-plane bend) instead of the conventional E-plane bend configuration. The H-plane bend structure has the potential for the production of high power, broad band radiation. For a cold beam, the linear theory predicts a gain of 2.0-2.5 dB/cm and a bandwidth of 20-25% in the millimeter wave frequencies. The bandwidth is sensitive to the axial velocity spread of the beam. The bandwidth decreases to 10% at δυzz=3%. Means to suppress the backward wave oscillations have to be applied for using the full bandwidth View full abstract»

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  • Base current reversal phenomenon in a CMOS compatible high gain n-p-n gated lateral bipolar transistor

    Page(s): 321 - 327
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (580 KB)  

    Base current reversal phenomenon is newly observed in a CMOS compatible high gain n-p-n gated lateral bipolar transistor. We attribute this phenomenon to avalanche generation as verified experimentally and by two-dimensional device simulation. Detailed investigation reveals that: (i) the multiplication ratio increases exponentially with the collector voltage or equivalently the peak field at the surface collector corner; and (ii) the multiplication ratio is independent of not only the low level base-emitter forward biases applied but also the base width of the transistors fabricated by the same process. Design guideline for suppression of the base current reversal has been established such as to fully realize the potential of the gated lateral bipolar transistors, i.e., a very high current gain of 11,600 can be maintained as long as the power supply voltage is less than the critical value of 1.78 V. On the other hand, new application directly employing this phenomenon has been suggested. Comparisons between the base current reversal phenomenon in the gated lateral bipolar transistor and that in the vertical bipolar transistor have also been performed and significant differences between the two have been drawn and have been adequately explained View full abstract»

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  • Long-term bias temperature reliability of P+ polysilicon gated FET devices

    Page(s): 360 - 362
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (260 KB)  

    An instability was found to be associated with +BT stress for P + poly-gated NMOSFETs (PNMOS) and PMOSFETs (PPMOS), but not with the N+ poly-gated devices (NNMOS and NPMOS). The instability with the P+ poly-gated devices, which is a decrease in threshold voltage (Vt) and an increase in interface state density (Dit), was significantly reduced following N2 annealing at 400°C. It is shown that adequate reliability for P+ poly-gated devices can be achieved for VLSI technologies View full abstract»

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  • Evaluation of the bonded silicon on insulator (SOI) wafer and the characteristics of PIN photodiodes on the bonded SOI wafer

    Page(s): 239 - 243
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (372 KB)  

    Electrical properties of the bonded silicon on insulator (SOI) wafer and characteristics of PIN photodiodes fabricated on the SOI layer were evaluated. A trap with deep energy level (about Ec-Et=0.55 eV) was observed in the SOI layer with 100 μm- and 30 μm-thickness using the deep level transient spectroscopy (DLTS) method. No trap was detected in the SOI layer with 10 μm-thickness. This deep trap was not observed before the wafer bonding process and thus the trap is generated during the wafer bonding process. From primary mode lifetime (τ1) measurements, it is considered that the trap will works as the generation center or the recombination center. For PIN photodiodes on the SOI layer in which the trap was detected, the increases of dark current were observed. Spectral responses of photodiodes on the SOI layer were almost the same as that on the normal FZ-Si wafer. We fabricated PIN photodiodes with good spectral response View full abstract»

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  • Low frequency noise characteristics of self-aligned AlGaAs/GaAs power heterojunction bipolar transistors

    Page(s): 219 - 230
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1008 KB)  

    The low frequency noise characteristics of modern self-aligned AlGaAs/GaAs power HBT's have been studied as a function of bias, temperature, frequency, and circuit topology. The devices have a 1/fγ behavior between 10 Hz and 100 Hz with 0.78⩽γ⩽1.65. Strong deviation from 1/fγ is measured at higher frequencies due to trapping. The bias dependence of the collector noise ranged from IC1.5-IC 2.6, while that for the base noise ranges from IB 0.7-IB2.5. In all cases the collector noise is greater than the base noise. The base noise is apparently dominated by surface recombination noise and generation-recombination (G-R) noise. The collector noise is due to recombination mechanisms and G-R noise. The activation energy (Ea ) of the most significant trap is approximately 0.58 eV. The noise of the devices tested was found to be dominated by material and fabrication related mechanisms and not by fundamental mechanisms View full abstract»

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  • Universality of electron mobility curves in MOSFETs: a Monte Carlo study

    Page(s): 258 - 265
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    The universal behavior of electron mobility when plotted versus the effective field is physically studied. Due to charged centers in the silicon bulk, the oxide, and the interface, Coulomb scattering is shown to be responsible for the deviation of mobility curves. Silicon bulk-impurities have a double effect: (a) Coulomb scattering due to the charge of these impurities themselves, and (b) reduction of screening caused by the loss of inversion charge when the depletion charge is increased. The electric-field region in which mobility curves behave universally regardless of bulk-impurity concentration, substrate bias, or interface charge has been determined for state-of-the-art MOSFETs. Finally, this study shows that electron mobility must be a function of the inversion and the depletion charges rather than a simple function of the effective field View full abstract»

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  • Finite element analysis of Hall effect and magnetoresistance

    Page(s): 328 - 333
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (436 KB)  

    This paper shows that the finite element method can be used to compute Hall voltages and electric fields, magnetoresistance, and current flow patterns. The computed Hall voltage is reduced (up to 54%) when the semiconductor geometry is changed from a narrow rod to a wide rod and when the sense electrodes are made of nonzero size. Both two-dimensional and three-dimensional geometries are analyzed View full abstract»

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  • Monolithic CCD imagers in HgCdTe

    Page(s): 244 - 250
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (776 KB)  

    Charge-coupled device (CCD) infrared detector arrays in 5 μm cutoff HgCdTe have been demonstrated for low background applications. These fully monolithic 128 by 28 element CCD arrays incorporate time-delay-and-integrate (TDI) detection, serial readout multiplexing, charge-to-voltage conversion and buffer amplification in the HgCdTe detector chip. Operation of these devices at 77 K have produced average detectivity values exceeding 3×1013 cm-Hz1/2/W for a background flux level of 6×1012 photon/cm2-sec in the 3.0 μm to 5.5 μm spectral band. Overall performance data indicates the monolithic HgCdTe CCD to be a promising alternative to present midwave infrared hybrid focal plane array technology View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology