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Computers, IEEE Transactions on

Issue 1 • Date Jan. 1995

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Displaying Results 1 - 18 of 18
  • An automaton model for scheduling constraints in synchronous machines

    Publication Year: 1995 , Page(s): 1 - 12
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1378 KB)  

    We present a finite-state model for scheduling constraints in digital system design. We define a two-level hierarchy of finite-state machines: a behavior FSM's input and output events are partially ordered in time; a register-transfer FSM is a traditional FSM whose inputs and outputs are totally ordered in time. Explicit modeling of scheduling constraints is useful for both high-level synthesis and verification-we can explicitly search the space of register-transfer FSM's which implement a desired schedule. State-based models for scheduling are particularly important in the design of control-dominated systems. This paper describes the BFSM I model, describes several important operations and algorithms on BFSM's and networks of communicating BFSM's, and illustrates the use of BFSM's in high-level synthesis.<> View full abstract»

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  • Degradable Byzantine agreement

    Publication Year: 1995 , Page(s): 146 - 150
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (516 KB)  

    Traditional Byzantine agreement protocols require all fault-free receivers to agree on an identical value. The proposed degradable agreement approach achieves traditional agreement up to m faults and a degraded form of agreement up to u faults (u⩾m), which allows fault-free receivers to agree on at most two different values (one of which is necessarily the default value). A degradable agreement algorithm and lower bounds are presented View full abstract»

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  • A remark on “Reducing iteration time when result digit is zero for radix-2 SRT division and square root with redundant remainders”

    Publication Year: 1995 , Page(s): 144 - 146
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (276 KB)  

    In a previous paper by P. Montuschi and L. Ciminiera (ibid., vol. 42, no.2 p239-246, Feb 1993), an architecture for shared radix 2 division and square root has been presented whose main characteristic is the ability to avoid any addition/subtraction, when the digit 0 has been selected. Here, we emphasize the characteristics of the digit selection mechanism used by Montuschi and Ciminiera by presenting a small modification of the digit selection hardware, which has the benefit to further reduce the computation delay with respect to the time estimated in that work View full abstract»

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  • Aliasing computation using fault simulation with fault dropping

    Publication Year: 1995 , Page(s): 139 - 144
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (584 KB)  

    It is generally thought that accurate analysis of aliasing requires non-fault dropping fault simulation. We show that fault dropping is possible when computing the exact aliasing of modeled faults for common output response compression circuits. The fault dropping process is most effective when the test set size is small. Extensions to large test sets are also considered. We present a fault simulation procedure that takes maximum advantage of fault dropping and present experimental results to support its effectiveness View full abstract»

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  • Wildcard dimensions, coding theory and fault-tolerant meshes and hypercubes

    Publication Year: 1995 , Page(s): 150 - 155
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (644 KB)  

    Hypercubes, meshes and tori are well known interconnection networks for parallel computers. The sets of edges in those graphs can be partitioned to dimensions. It is well known that the hypercube can be extended by adding a wildcard dimension resulting in a folded hypercube that has better fault-tolerant and communication capabilities. First we prove that the folded hypercube is optimal in the sense that only a single wildcard dimension ran be added to the hypercube. We then investigate the idea of adding wildcard dimensions to d-dimensional meshes and tori. Using techniques from error correcting codes we construct d-dimensional meshes and tori with wildcard dimensions. Finally, we show how these constructions can be used to tolerate edge and node faults in mesh and torus networks View full abstract»

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  • A new public-key cipher system based upon the diophantine equations

    Publication Year: 1995 , Page(s): 13 - 19
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (612 KB)  

    A new public-key (two-key) cipher scheme is proposed in this paper. In our scheme, keys can be easily generated. In addition, both encryption and decryption procedures are simple. To encrypt a message, the sender needs to conduct a vector product of the message being sent and the enciphering key. On the other hand, the receiver can easily decrypt it by conducting several multiplication operations and modulus operations. For security analysis, we also examine some possible attacks on the presented scheme View full abstract»

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  • Routing in a three-dimensional chip

    Publication Year: 1995 , Page(s): 106 - 117
    Cited by:  Papers (14)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1000 KB)  

    As the very large scale integration (VLSI) technology approaches its fundamental scaling limit at about 0.2 μm, it is reasonable to consider three-dimensional (3-D) integration to enhance packing density and speed performance. With additional functional units packed into one chip in a 3-D space, computer-aided design (CAD) tools are demanded to ease the complicated design work. This paper presents a 100% completion achievable routing methodology. The routing methodology is based on the two-dimensional (2D) channel routing methodology; thus, it is called a 3-D channel routing methodology. With the routing methodology, a 3-D routing problem is decomposed into two 2D routing subproblems: intra-layer routing that interconnects terminals on the same layer, which can be done by using a 2-D channel router, and inter-layer routing that interconnects terminals on different layers. The inter-layer routing problem is transformed into a 2-D channel routing problem and the transformation is made in some 3-D channels. Detailed discussions are given for the 3-D to 2-D transformation. Optimization of the transformation is shown to be NP-complete. Thus, simulated annealing is used to optimize the transformation View full abstract»

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  • On memory contention problems in vector multiprocessors

    Publication Year: 1995 , Page(s): 92 - 105
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1056 KB)  

    Memory interleaving considerably increases memory bandwidth in vector processor systems. The concurrent operation of the processors can produce memory bank conflicts and hence alter the memory bandwidth. Total or steady state performance for vector operations in a memory system is studied. Many methods of resolving memory bank conflicts are proposed and compared. Analytical results on the resulting effective bandwidth are presented for one of them and the others are described by exhaustive simulations. Some nonintuitive results are obtained on how conflicts depend on the size of the architecture, the number, the stride and the length of the vectors, the register length assigned by each processor to vector components View full abstract»

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  • The stochastic rendezvous network model for performance of synchronous client-server-like distributed software

    Publication Year: 1995 , Page(s): 20 - 34
    Cited by:  Papers (64)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1284 KB)  

    Distributed or parallel software with synchronous communication via rendezvous is found in client-server systems and in proposed open distributed systems, in implementation environments such as Ada, V, remote procedure call systems, in transputer systems, and in specification techniques such as CSP, CCS and LOTOS. The delays induced by rendezvous can cause serious performance problems, which are not easy to estimate using conventional models which focus on hardware contention, or on a restricted view of the parallelism which ignores implementation constraints. Stochastic rendezvous networks are queueing networks of a new type which have been proposed as a modelling framework for these systems. They incorporate the two key phenomena of included service and a second phase of service. This paper extends the model to also incorporate different services or entries associated with each task. Approximations to arrival-instant probabilities are employed with a mean-value analysis framework, to give approximate performance estimates. The method has been applied to moderately large industrial software systems View full abstract»

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  • On the conversion between binary code and binary-reflected Gray code on binary cubes

    Publication Year: 1995 , Page(s): 47 - 53
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (684 KB)  

    We present a new algorithm for conversion between binary code and binary-reflected Gray code that requires approximately 2 K/3 element transfers in sequence for K elements per node, compared to K element transfers for previously known algorithms. For a binary cube of n=2 dimensions the new algorithm degenerates to yield a complexity of 2 K/+1 element a transfers, which is optimal. The new algorithm is optimal to within a multiplicative factor of 4/3 with respect to the best known 3 lower bound for any routing strategy. We show that the minimum number of element transfers for minimum path length routing is K with concurrent communication on all channels of every node of a binary cube View full abstract»

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  • Single residue error correction based on K-term mj-projection

    Publication Year: 1995 , Page(s): 129 - 131
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB)  

    In the literature, mj-projection has been applied for residue error detection and correction. This brief contribution extends the mj projection to K-term mj-projection so that single residue error correction can be accomplished in an efficient manner. Based on K-term mj projection, the necessary and sufficient conditions for the correction of single residue digit error are derived and an efficient procedure for single error correction is given View full abstract»

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  • Compiler-based multiple instruction retry

    Publication Year: 1995 , Page(s): 35 - 46
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (996 KB)  

    This paper describes a compiler-based approach to provide multiple instruction rollback capability for general purpose processor registers. The objective is achieved by having the compiler remove all forms of N-instruction antidependencies. Pseudoregister antidependencies are removed by loop protection, node splitting, and loop expansion techniques; machine register antidependencies are prevented by introducing antidependency constraints in the interference graph used by the register allocator. To support separate compilation, inter-procedural antidependency constraints are added to the code generator to guarantee the termination of machine register antidependencies across procedure boundaries. The algorithms have been implemented in the IMPACT C compiler. Experiments illustrating the effectiveness of this approach are described View full abstract»

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  • A design of Reed-Solomon decoder with systolic-array structure

    Publication Year: 1995 , Page(s): 118 - 122
    Cited by:  Papers (12)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (332 KB)  

    This brief contribution proposes a new class of systolic-arrays to perform Binary Reed-Solomon (RS) decoding procedures including erasure correction. Such RS decoder is suitable for VLSI implementation since the arrays consist of simple processing elements of the same type View full abstract»

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  • Formal modeling and verification of microprocessors

    Publication Year: 1995 , Page(s): 54 - 72
    Cited by:  Papers (13)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1684 KB)  

    This paper presents a methodology for microprocessor verification that significantly reduces the learning curve for performing verification. The methodology is formalized in the HOL theorem-proving system. The paper includes a description of a large case study performed to evaluate the methodology. The novel aspects of this research include the use of abstract theories to formalize hardware models. Because our model is described using abstract theories, it provides a framework for both the specification and the verification. This framework reduces the number of ad hoc modeling decisions that must be made to complete the verification. Another unique aspect of our research is the use of hierarchical abstractions to reduce the number of difficult lemmas in completing the verification. Our formalism frees the user from directly reasoning about the difficult aspects of modeling the hierarchy, namely the temporal and data abstractions. We believe that our formalism, coupled with case studies and tools, allows microprocessor verification to be done by engineers with relatively little experience in microprocessor specification or logic. We are currently testing that hypothesis by using the methodology to teach graduate students formal microprocessor modeling View full abstract»

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  • The Connection Network class for Fault Tolerant Meshes

    Publication Year: 1995 , Page(s): 131 - 138
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (764 KB)  

    The Connection Network is a new class of Fault Tolerant Mesh networks which uses a switched bus net in a mesh-connected array. Much use of Rail Networks for Fault Tolerance of WSI is reported in the literature. The Connection Network simplifies the Rail Networks, and is superior in terms of theoretical power to survive faults. We demonstrate this by general comparison of the Connection and Rail Classes of networks, and a specific comparison between the Single Connection, Double Rail and Symmetric Networks. Our results show that the Connection Network is more powerful in terms of statistical theoretical constants and flexibility of algorithms; comparable in terms of VLSI area usage; has less signal delay on interconnections between Processing Elements; facilitates the implementation of switches which are fault tolerant and gracefully degradable; and allows the addition of redundant rails to cope with wire failure View full abstract»

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  • New bounds on the reliability of augmented shuffle-exchange networks

    Publication Year: 1995 , Page(s): 123 - 129
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (632 KB)  

    The reliability resulting from two forms of redundancy, spatial and temporal, in multistage interconnection networks is examined. The extra-stage shuffle-exchange network (SEN+) which is an example of the former is investigated here. The SEN+ is decomposed into two subnetworks connected by two extreme stages. Given k random faults in one subnetwork, our problem reduces to estimating the maximum and minimum number of switches in the other subnetwork that must be operational for full access, i.e., connection between every input (processor) and output (memory) pair. This investigation results in obtaining analytical estimates for the upper and lower bounds on its reliability which are a substantial improvement over existing ones. We next examine the effect of wrap-around connections from each output node to its corresponding input node. This may provide a path between a source-destination pair under faults by diverting a given packet through one or more intermediate destinations. The reliability offered by this scheme that provides temporal redundancy is also estimated and compared with the scheme employing hardware redundancy View full abstract»

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  • Implementation of four common functions on an LNS co-processor

    Publication Year: 1995 , Page(s): 155 - 161
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (560 KB)  

    We propose a scheme for evaluating four commonly used functions namely, (1) inverse trigonometric functions, (2) trigonometric functions, (3) the exponential function, and (4) the logarithmic function with the help of a logarithmic number system (LNS) processor. A novel idea of series folding has been introduced for computing the above functions, expressed in the form of infinite series. We also show that with a suitable choice of the radix for the LNS we can evaluate exponential and logarithmic functions without using any extra hardware View full abstract»

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  • The deferrable server algorithm for enhanced aperiodic responsiveness in hard real-time environments

    Publication Year: 1995 , Page(s): 73 - 91
    Cited by:  Papers (126)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1616 KB)  

    Most existing scheduling algorithms for hard real-time systems apply either to periodic tasks or aperiodic tasks but not to both. In practice, real-time systems require an integrated, consistent approach to scheduling that is able to simultaneously meet the timing requirements of hard deadline periodic tasks, hard deadline aperiodic (alert-class) tasks, and soft deadline aperiodic tasks. This paper introduces the Deferrable Server (DS) algorithm which will be shown to provide improved aperiodic response time performance over traditional background and polling approaches. Taking advantage of the fact that, typically, there is no benefit in early completion of the periodic tasks, the Deferrable Server (DS) algorithm assigns higher priority to the aperiodic tasks up until the point where the periodic tasks would start to miss their deadlines. Guaranteed alert-class aperiodic service and greatly reduced response times for soft deadline aperiodic tasks are important features of the DS algorithm, and both are obtained with the hard deadlines of the periodic tasks still being guaranteed. The results of a simulation study performed to evaluate the response time performance of the new algorithm against traditional background and polling approaches are presented. In all cases, the response times of aperiodic tasks are significantly reduced (often by an order of magnitude) while still maintaining guaranteed periodic task deadlines View full abstract»

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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org