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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 1 • Date March 1995

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Displaying Results 1 - 13 of 13
  • Optimum and heuristic transformation techniques for simultaneous optimization of latency and throughput

    Publication Year: 1995, Page(s):2 - 19
    Cited by:  Papers (27)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1878 KB)

    Although throughput alone can be arbitrarily improved for several classes of systems using previously published techniques, none of those approaches are effective when latency constraints, which are increasingly important in embedded DSP systems, are considered. After formally establishing the relationship between latency and throughput in general computation, we explore the effect of pipelining o... View full abstract»

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  • System level hardware module generation

    Publication Year: 1995, Page(s):20 - 35
    Cited by:  Papers (9)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1965 KB)

    In complex modern day electronic systems, far more time is spent in designing the boards, writing the software to drive and integrate the hardware, and other such system level issues, than is spent in designing any application-specific ICs that may be needed. Unfortunately, most of the research in computer-aided design has been focussed on the more glamorous ASIC design problem, as a result of whi... View full abstract»

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  • Design and realization of high-performance wave-pipelined 8/spl times/8 b multiplier in CMOS technology

    Publication Year: 1995, Page(s):36 - 48
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1163 KB)

    Wave pipelining is a design technique for increasing the throughput of a digital circuit or system without introducing pipelining registers between adjacent combinational logic blocks in the circuit/system. However, this requires balancing of the delays along all the paths from the input to the output which comes the way of its implementation. Static CMOS is inherently susceptible to delay variati... View full abstract»

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  • Bus-invert coding for low-power I/O

    Publication Year: 1995, Page(s):49 - 58
    Cited by:  Papers (493)  |  Patents (108)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1007 KB)

    Technology trends and especially portable applications drive the quest for low-power VLSI design. Solutions that involve algorithmic, structural or physical transformations are sought. The focus is on developing low-power circuits without affecting too much the performance (area, latency, period). For CMOS circuits most power is dissipated as dynamic power for charging and discharging node capacit... View full abstract»

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  • Testing complex couplings in multiport memories

    Publication Year: 1995, Page(s):59 - 71
    Cited by:  Papers (31)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1397 KB)

    In this paper, the effects of simultaneous write access on the fault modeling of multiport RAMs are investigated. New fault models representing more accurately the actual faults in such memories are then defined. Subsequently, a general algorithm that ensures the detection of all faults belonging to the new fault model is proposed. Unfortunately, the obtained algorithms are of O(n/sup 2/) complexi... View full abstract»

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  • Cumulative balance testing of logic circuits

    Publication Year: 1995, Page(s):72 - 83
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1207 KB)

    We present a new test response compression method called cumulative balance testing (CBT) that extends both balance testing and accumulator compression testing. CBT uses an accumulated balance signature, and it guarantees very high error coverage (over 99%) for various error models. We demonstrate that the single stuck-line (SSL) fault coverage of CBT for many of the ISCAS 85 combinational benchma... View full abstract»

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  • A buffer distribution algorithm for high-performance clock net optimization

    Publication Year: 1995, Page(s):84 - 98
    Cited by:  Papers (9)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1519 KB)

    We propose a new approach for optimizing clock trees, especially for high-speed circuits. Our approach provides a useful guideline to a designer, by user-specified parameters, and three of these tradeoffs are provided in this paper. (1) First, to provide a "good" tradeoff between skew and wire length, a new clock tree routing scheme is proposed. The technique is based on a combination of hierarchi... View full abstract»

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  • A unified design methodology for CMOS tapered buffers

    Publication Year: 1995, Page(s):99 - 111
    Cited by:  Papers (66)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1431 KB)

    In this paper, the various disparate approaches to CMOS tapered buffer design are unified into an integrated design methodology. Circuit speed, power dissipation, physical area, and system reliability are the four performance criteria of concern in tapered buffers, and each places a separate, often conflicting, constraint on the design of a tapered buffer. Enhanced short-channel tapered buffer des... View full abstract»

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  • A practical methodology for the statistical design of complex logic products for performance

    Publication Year: 1995, Page(s):112 - 123
    Cited by:  Papers (24)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1575 KB)

    Contradictory trends in the industrial design environment have increased uncertainty while decreasing the tolerance to uncertainty. Worst case design techniques, still widely used in industry, do not provide the accuracy required to design under these conditions. On the other hand, statistical design techniques do provide a significant improvement in accuracy, by virtue of their "circuit adaptive"... View full abstract»

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  • Physical models and algorithms for optoelectronic MCM layout

    Publication Year: 1995, Page(s):124 - 135
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1365 KB)

    Future computers will need to incorporate the parallelism of optical interconnections in order to achieve projected performance within reasonable size, power and speed constraints. This is necessary since optical interconnections have advantages in size, power, and speed over "long" distance communication. These features make optical interconnects ideal for inter-module connections in multichip mo... View full abstract»

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  • An architecture for a DSP field-programmable gate array

    Publication Year: 1995, Page(s):136 - 141
    Cited by:  Papers (5)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (533 KB)

    This paper describes an application specific architecture for field-programmable gate arrays (FPGAs). Emphasis is placed on the logic module architecture and channel segmentation for the FPGAs targeted for application areas related to digital signal processing (DSP). The proposed logic module architecture is well-suited for efficient implementation of frequently used logic functions in the DSP app... View full abstract»

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  • On general zero-skew clock net construction

    Publication Year: 1995, Page(s):141 - 146
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB)

    We propose a simulated annealing based zero-skew clock net construction algorithm that works in any routing spaces, from Manhattan to Euclidean, with the added flexibility of optimizing either the wire length or the propagation delay. We first devise an O(log n) tree grafting perturbation function to construct a zero-skew clock tree under the Elmore delay model. This tree grafting scheme is able t... View full abstract»

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  • C-testable design techniques for iterative logic arrays

    Publication Year: 1995, Page(s):146 - 152
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (663 KB)

    A design-for-testability (DFT) approach for VLSI iterative logic arrays (ILA's) is proposed, which results in a small constant number of test patterns. Our technique applies to arrays with an arbitrary dimension, and to arrays with various connection types, e.g., hexagonal or octagonal ones. Bilateral ILA's are also discussed. The DFT technique makes general ILA's C-testable by using a truth-table... View full abstract»

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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu