Issue 1 • Date March 1995
Filter Results
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Optimum and heuristic transformation techniques for simultaneous optimization of latency and throughput
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PDF (1878 KB)
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System level hardware module generation
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PDF (1965 KB)
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Design and realization of high-performance wave-pipelined 8/spl times/8 b multiplier in CMOS technology
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PDF (1163 KB)
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Bus-invert coding for low-power I/O
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PDF (1007 KB)
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Testing complex couplings in multiport memories
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PDF (1397 KB)
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Cumulative balance testing of logic circuits
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PDF (1207 KB)
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A practical methodology for the statistical design of complex logic products for performance
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PDF (1575 KB)
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On general zero-skew clock net construction
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PDF (648 KB)
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Aims & Scope
IEEE Transactions on Very Large Scale Integration (VLSI) Systems includes all major aspects of the design and implementation of VLSI/ULSI and microelectronic systems.
Meet Our Editors
Editor-in-Chief
Yehea Ismail
CND Director
American University of Cairo and Zewail City of Science and Technology
New Cairo, Egypt
tvlsieic@eecs.northwestern.edu


