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Electron Device Letters, IEEE

Issue 3 • Date March 1995

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Displaying Results 1 - 13 of 13
  • The drain threshold voltage VTd in submicrometer MOS transistors at 4.2 K

    Publication Year: 1995 , Page(s): 85 - 87
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (212 KB)  

    In this paper a set of experimental results of the so-called drain threshold voltage V/sub Td/, and its impact on the electrical performance of submicrometer MOS transistors, are presented. This effect is more pronounced when the device is operated in a cryogenic ambient. Therefore, by reducing the temperature down to 4.2 K, the V/sub Td/ mechanism, which is not visible at room temperature, is amplified and more easily related to the negative overlapping source-gate length (-/spl Delta/L). In this way it is found that the devices with a larger V/sub Td/ are the ones with a more negative /spl Delta/L, showing that the V/sub Td/ and the -/spl Delta/L are correlated and have the same physical origin. Moreover, it is suspected that the reverse short-channel effect (RSCE) might be also correlated to the V/sub Td/ effect.<> View full abstract»

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  • A scaled, high-performance (4.5 fJ) bipolar device in a 0.35 μm high-density BiCMOS SRAM technology

    Publication Year: 1995 , Page(s): 88 - 90
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (251 KB)  

    We present the performance improvements obtained both by scaling the Selectively Compensated Collector (SCC) BJT and by using a modified Current-Mode Logic (CML) gate configuration. Scaling the perimeter parameter by using the (tighter) bitcell design rules results in a /spl sim/30% reduction in parasitic capacitances, and a 23% lower power-delay product; reducing it from 48 fJ to 37 fJ. The greatest return comes from using a modified CML gate, which has an n-MOS current source. At a supply voltage of 1.1 V, and at 40 μA switching current, the minimum power-delay product of this CML gate is a silicon-substrate bipolar record 4.5 fJ. View full abstract»

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  • A measurement method of the injection dependence of the conductivity mobility in silicon

    Publication Year: 1995 , Page(s): 91 - 93
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (285 KB)  

    A new electrical method to measure the conductivity mobility as a function of the injection level is proposed in this paper. The measurement principle is based on the detection of the voltage drop appearing across a n/sup +/-n-n/sup +/ (p/sup +/-p-p/sup +/) structure when a current step is forced into it at a given injection level in the intermediate region. This is obtained by using a three-terminal test pattern consisting of p/sup +/, n/sup +/ layers realized on top of a n-n/sup +/ (p-p/sup +/) epitaxial wafer, where the p/sup +/-n-n/sup +/ (n/sup +/-p-p/sup +/) surface diode is forward biased to monitor the conductivity of the epilayer. The use of separate terminals for injection control and mobility measurement allows this technique to overcome some limitations presented by other electrical methods available in literature, Mobility values measured up to 2/spl middot/10/sup 17/ cm/sup -3/ are in good agreement with those predicted by the Dorkel and Leturcq's model (1981).<> View full abstract»

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  • Reduction of threshold voltage sensitivity in SOI MOSFET's

    Publication Year: 1995 , Page(s): 100 - 102
    Cited by:  Papers (10)  |  Patents (84)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (271 KB)  

    The threshold voltage sensitivity, of fully depleted SOI MOSFET's to variations in SOI silicon film thickness was examined through both simulation and device experiments. The concept of designing the channel V/sub th/ implant to achieve a constant dose within the film, rather than a constant doping concentration, was studied for a given range of film thicknesses. Minimizing the variation in retained dose reduced the threshold voltage sensitivity to film thickness for the range of t/sub si/ examined. One-dimensional process simulations were performed to determine the optimal channel implant condition that would reduce the variation in retained dose using realistic process parameters for both NMOS and PMOS device processes. SOI NMOS transistors were fabricated. The experimental results confirmed the simulation findings and achieved a reduced threshold voltage sensitivity.<> View full abstract»

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  • 7-μm-cutoff PtSi infrared detector for high sensitivity MWIR applications

    Publication Year: 1995 , Page(s): 94 - 96
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (226 KB)  

    PtSi Schottky infrared detectors with extended cutoff wavelengths of 5.7, 6.6, and 7.3 μm have been demonstrated by incorporating a thin p+ layer at the PtSi-Si interface for high sensitivity medium wavelength infrared imaging applications. The response uniformity of the 7-μm cutoff detector was studied. View full abstract»

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  • High emitter efficiency in InP/GaInAs HBT's with ultra high base doping levels

    Publication Year: 1995 , Page(s): 97 - 99
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB)  

    The emitter efficiency of InP/GaInAs heterojunction bipolar transistors is calculated taking into account bandgap narrowing in the base, quantum mechanical tunneling, and the exact doping profile in the base. It is found that the emitter efficiency is high and does not limit the current gain of practical devices, up to a base doping level of 1/spl times/10/sup 20/ cm/sup -3/, and up to 400/spl deg/K . It is shown that the base emitter junction saturation current can be controlled over two orders of magnitude by a proper small displacement of the doped layer in the base.<> View full abstract»

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  • Low frequency gate current noise in high electron mobility transistors: experimental analysis

    Publication Year: 1995 , Page(s): 103 - 105
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (267 KB)  

    An experimental investigation on the gate current noise in a pseudomorphic HEMT has been carried out. The measurements have been performed from 10 Hz to 100 kHz, at different bias conditions. It is shown that the noise spectral power density strongly depends on the biasing point and can be explained in terms of carrier trapping phenomena by means of packets of Lorentzian components.<> View full abstract»

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  • High-speed metal-semiconductor-metal photodiodes with Er-doped GaAs

    Publication Year: 1995 , Page(s): 106 - 108
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB)  

    Very high-speed MSM photodiodes have been fabricated on Er-doped GaAs over a doping range of 10/sup 18/-10/sup 20/ cm/sup -3/. The impulse response (characterized by photoconductive sampling) of these diodes, with finger widths/spacings of 2 μm, has been found to be tunable over a range of about 3 ps-22 ps. Electro-optic sampling was used to characterize MSM diodes with finger widths/spacings of 0.5 μm and 1 μm on a sample with [Er]=10/sup 19/ cm/sup -3/, resulting in 3-dB bandwidths of 160 GHz and 140 GHz, respectively, corresponding to pulse widths of 2.7 ps and 3.3 ps. Correlation measurements were also done on the GaAs:Er samples, using an all-electronic Sampling Optical Temporal Analyzer (SOTA) structure. View full abstract»

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  • Enhancement mode InP MISFET's with sulfide passivation and photo-CVD grown P3N5 gate insulators

    Publication Year: 1995 , Page(s): 109 - 111
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (309 KB)  

    High performance enhancement mode InP MISFET's have been successfully fabricated by using the sulfide passivation for lower interface states and with photo-CVD grown P/sub 3/N/sub 5/ film used as gate insulator. The MISFET's thus fabricated exhibited exhibited pinch-off behavior with essentially no hysteresis. Furthermore the device showed a superior stability of drain current. Specifically under the gate bias of 2 V for 10/sup 4/ seconds the room temperature drain current was shown to reduce from the initial value merely by 2.9% at the drain voltage of 4 V. The effective electron mobility and extrinsic transconductance are found to be about 2300 cm/sup 2V/spl middot/s and 2.7 mS/mm, respectively. The capacitance-voltage characteristics of the sulfide passivated InP MIS diodes show little hysteresis and the minimum density of interface trap states as low as 2.6/spl times/10/sup 14cm/sup 2/ eV has been attained.<> View full abstract»

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  • A novel /spl delta/-doped GaAs/lnGaAs real-space transfer transistor with high peak-to-valley ratio and high current driving capability

    Publication Year: 1995 , Page(s): 112 - 114
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (326 KB)  

    A three-terminal /spl delta/-doped GaAs/In/sub 0.25/Ga/sub 0.75/As/GaAs real-space transfer transistor (RSTT) has been implemented by low-pressure metalorganic chemical vapor deposition (LP-MOCVD) for the first time. We carried out an ohmic recess resulting in shallow alloyed contacts, electrically isolated from ohmic electrodes. An undoped low-growth-rate buffer layer was inserted between the collector and barrier to suppress the dopant out-diffusion from the substrate to the barrier. The proposed device with a 5×100 μm2 emitter channel revealed an extremely sharp charge injection, a broad valley range (>5 V), a high peak-to-valley current ratio up to 430000, and a high current driving capability at room temperature. These characteristics are, to our knowledge, among the highest reported values to date. View full abstract»

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  • A new three-terminal switching device

    Publication Year: 1995 , Page(s): 115 - 117
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (252 KB)  

    A new switching device has been conceived and reduced to practice. This device is a once-programmable three-terminal fuse (TTF) with an on-resistance of a good metallic conductor and an off-resistance which is essentially infinite. In the new structure the fusible circuit path is fully isolated from a control electrode both before and after programming. We discuss the basic concept of the TTF and highlight some of its possible applications.<> View full abstract»

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  • 2-D dopant profiling in VLSI devices using dopant-selective etching: an atomic force microscopy study

    Publication Year: 1995 , Page(s): 118 - 120
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (297 KB)  

    We report a detailed mapping of a 2-D dopant profile on a fully processed industrial sample with large dynamic range and high spatial resolution by utilizing a dopant-selective etching process and Atomic Force Microscopy. The experimental results show excellent agreement with those obtained from SRP and SIMS as corroborative methods. We also discuss the most critical factors which influence the applicability, reproducibility, and reliability of this method.<> View full abstract»

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  • New operation mode for stacked-gate flash memory cell

    Publication Year: 1995 , Page(s): 121 - 123
    Cited by:  Papers (2)  |  Patents (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (236 KB)  

    A new operational mode is proposed that lowers the threshold voltage of a stacked-gate flash memory cell. The mode features the set-up of the word-line voltage and bit-line voltage. An AC signal is applied to a word-line while a bit-line is kept floating after it is charged. The signal is applied to lower the threshold voltage of the cell and to test it. A SPICE simulation of this operation has revealed that the converged voltage of floating gate has negligible dependency on the initial voltage and the tunnel oxide thickness and that the cell threshold voltage is controllable through the world-line voltage. This operation mode is easily applicable to a conventional flash memory. Furthermore, it may allow the use of flash cells in analog applications or in multi-level memory cells.<> View full abstract»

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IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

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