IEEE Design & Test of Computers

Issue 1 • Feb. 1989

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Displaying Results 1 - 6 of 6
  • Wafer-level testing with a membrane probe

    Publication Year: 1989, Page(s):10 - 17
    Cited by:  Papers (22)  |  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (656 KB)

    The authors describe a proprietary membrane probe card that addresses the needs of testing VLSI devices at the wafer level. The membrane probe allows the testing of devices with a high pin count at operating speed, while allowing a complete package test at the wafer level. The concepts and structure of the probe are examined, and its performance is demonstrated by time-domain and frequency-domain ... View full abstract»

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  • An ultra high speed test system

    Publication Year: 1989, Page(s):18 - 24
    Cited by:  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (473 KB)

    The test-head subsystem presented uses gallium arsenide pin electronics to provide nonrepeating zero data rates up to 1.2 Gb/s. The device under test is connected to laser-scanned optical sensors, and the test system receivers use an electrooptic measurement method to capture the pin information. The receiver has a 4.5-GHz bandwidth and can perform functional test at the emitter-coupled logic leve... View full abstract»

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  • Realistic built-in self-test for static RAMs

    Publication Year: 1989, Page(s):26 - 34
    Cited by:  Papers (26)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (741 KB)

    The authors present the specification and design of a self-test mechanism for static random-access memories (RAMs). The test algorithm provides excellent fault detection, and its structure is independent of address and data scrambling. The self-test machine generates data backgrounds on chip and is therefore suitable for both bit-oriented and word-oriented SRAMs. It is also suitable for both embed... View full abstract»

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  • Boundary scan with built-in self-test

    Publication Year: 1989, Page(s):36 - 44
    Cited by:  Papers (25)  |  Patents (12)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (678 KB)

    The authors propose a way to merge boundary scan with the built-in self-test (BIST) of printed circuit boards. Their boundary-scan structure is based on Version 2.0 of the Joint Task Action Group's recommendations for boundary scan and incorporates BIST using a register based on cellular automata (CA) techniques. They examine test patterns generated from this register and the more conventional lin... View full abstract»

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  • A statistical model for delay-fault testing

    Publication Year: 1989, Page(s):45 - 55
    Cited by:  Papers (24)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (833 KB)

    The authors propose a statistical model for measuring delay-fault coverage. The model provides a figure of merit for delay testing in the same way that fault coverage provides one for the testing of single stuck-at faults. The mode measures test effectiveness in terms of the propagation delay of the path to be tested, the size of the delay defect, and the system clock interval, and then combines t... View full abstract»

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  • Post-layout verification of the WE DSP32 digital signal processor

    Publication Year: 1989, Page(s):56 - 66
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (839 KB)

    The authors describe the successful postlayout verification of the WE DSP32 digital signal processor and the application of advanced CAD (computer-aided design) tools. The development work culminated in the smooth transfer of the DSP32 design into high-volume production. During this period, the authors were able to diagnose and repair hundreds of design errors. They also caught errors in the test-... View full abstract»

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This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Krishnendu Chakrabarty