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Computers and Digital Techniques, IEE Proceedings -

Issue 1 • Date Jan 1995

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Displaying Results 1 - 11 of 11
  • Associative memory architecture for video compression

    Publication Year: 1995 , Page(s): 55 - 64
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (676 KB)  

    Video compression is becoming increasingly important, with several applications. There are two kinds of redundancies in a video sequence, namely spatial and temporal. Vector quantisation (VQ) is an efficient technique for exploiting spatial correlation. Temporal redundancies are usually removed by using motion estimation/compensation techniques. The coding performance of VQ may be improved by employing adaptive techniques at the expense of increases in computational complexity. Both VQ and motion estimation algorithms are essentially template matching operations. However, they are computer intensive, necessitating the use of special-purpose architectures for real-time implementation. The authors propose a unified associative memory architecture for real-time implementation of motion estimation and frame-adaptive vector quantisation for video compression. The proposed architecture has the advantage of simplicity, partitionability and modularity and has hence the potential for VLSI implementation View full abstract»

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  • Integrated scheduling, allocation and module selection for design-space exploration in high-level synthesis

    Publication Year: 1995 , Page(s): 65 - 71
    Cited by:  Papers (13)  |  Patents (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (448 KB)  

    High-level synthesis consists of many interdependent tasks such as scheduling, allocation and binding. To make efficient use of time and area, functional unit allocation must be performed using a library of modules which contains a variety of module types with identical functionality, but different area and delay characteristics. The synthesis technique presented in the paper simultaneously performs scheduling, allocation and module selection, using problem-space genetic algorithm (PSGA) to produce area and performance optimised designs. The PSGA-based system uses an intelligent design-space exploration technique by combining a genetic algorithm with a simple and fast problem-specific heuristic to search a large design space effectively and efficiently. The efficient exploration of design-space is essential to design cost-effective architectures for problems of VLSI/ULSI complexity. The PSGA method offers several advantages such as the versatility, simplicity, objective independence and the computational advantages for problems of large size over other existing techniques. The proposed synthesis system handles multicycle functional units, chaining, conditional constructs, loops and structural pipelining. Experiments on benchmarks show very promising results View full abstract»

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  • New class of t-error correcting and all unidirectional error detecting (t-EC/AUED) codes

    Publication Year: 1995 , Page(s): 32 - 40
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (384 KB)  

    A new class of t-error correcting and all unidirectional error detecting (t-EC/AUED) codes with reduced number of check bits is presented. The encoding/decoding algorithms for this class of codes can be implemented with faster as well as simpler hardware. The ROM implementation of the proposed scheme results in significant saving of word length View full abstract»

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  • Optimising a high-speed serial/parallel sum-of-products hardware structure with respect to bus utilisation

    Publication Year: 1995 , Page(s): 77 - 80
    Cited by:  Papers (2)  |  Patents (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (256 KB)  

    A novel high-speed serial/parallel (S/P) sum-of-products (SOP) hardware structure, based on two's complement number coding, as well as the mathematical framework needed when optimising the hardware structure with respect to bus utilisation is presented. The hardware blocks necessary to obtain a regular and efficient circuit structure are described. The SOP hardware structure basically consists of a modified S/P multiplier, performing inner-product computations, and a novel partitioned accumulator, which can always be designed sufficiently large for any application. Estimations of performance/area-cost ratio show that the proposed SOP hardware structure is superior to conventional S/P multiplication-accumulation hardware in most situations View full abstract»

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  • Quotient prediction without prescaling

    Publication Year: 1995 , Page(s): 15 - 22
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (572 KB)  

    The paper analyses an SRT radix-B division algorithm where the determination of the quotient digits is performed in parallel with the updating of the residual. The authors do not use any prescaling digit prediction (in order to reduce the complexity of the selection function) as it is done using other prediction-based techniques. The authors present application examples of radix-2 (and radix-4, briefly) division design using their prediction scheme, and compare them with the `classical' SRT radix-2, radix-4 and radix-16 schemes without prediction. They estimate that the proposed algorithm achieves execution times comparable to the computation delay of the `classical' SRT radix-B 2 division algorithm without prediction, but requires less hardware View full abstract»

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  • SOLiT: An automated system for synthesising reliable sequential circuits with multilevel logic implementation

    Publication Year: 1995 , Page(s): 49 - 54
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (596 KB)  

    The paper presents SOLiT, an automated system for synthesising reliable sequential circuits with multilevel logic implementation. The reliability enhancement is achieved by using concurrent error detection scheme with coding techniques. The system receives the behavioural description of finite-state machines, determines the required checker circuits, and generates the physical layouts. The synthesised circuits can detect multiple unidirectional errors. A novel output partitioning algorithm is presented to reduce the hardware cost of the required checker circuits. Results show that the overhead for reliability enhancement of the synthesised sequential circuits is relatively low View full abstract»

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  • CONVERGE: a circular-assignment-based switchbox router with via reduction

    Publication Year: 1995 , Page(s): 72 - 76
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (384 KB)  

    The authors propose a new circular assignment-based switchbox router, CONVERGE, based on segment assignment in circular routing. The CONVERGE router is divided into three phases: the iterative phase, the merging phase and the via reduction phase. In the iterative phase, circular routing will be applied to assign vertical or horizontal segments cycle by cycle. In the merging phase, if switchbox routing is successful, the routing result can be further improved by merging adjacent segments of the same routing net. Finally, in the via reduction phase, constrained layer assignment can further reduce the number of vias. As a result, many benchmarks have been tested on the switchbox router, and these benchmarks are successfully routed. In addition, the proposed switchbox router has better routing results than other switchbox routers on vias and wire length View full abstract»

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  • A star-based I/O-bounded network for massively parallel systems

    Publication Year: 1995 , Page(s): 5 - 14
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (752 KB)  

    The paper describes a new interconnection network for massively parallel systems, referred to as star-connected cycles (SCC). The SCC graph presents an I/O-bounded structure that results in several advantages over variable degree graphs like the star and the hypercube. The description of the SCC graph includes issues such as labelling of nodes, degree, diameter and symmetry. The paper also presents an optimal routeing algorithm for the SCC and efficient broadcasting algorithms with O(n) running time, with n being the dimensionality of the graph. A comparison with the cube-connected cycles (CCC) and other interconnection networks is included, indicating that, for even n, an n-SCC and a CCC of similar sizes have about the same diameter. In addition, it is shown that one-port broadcasting in an n-SCC graph can be accomplished with a running time better than or equal to that required by an n-star containing (n-1) times fewer nodes View full abstract»

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  • Test time reduction for scan-designed circuits by sliding compatibility

    Publication Year: 1995 , Page(s): 41 - 48
    Cited by:  Patents (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (548 KB)  

    A postgeneration method for test time reduction of scan-designed circuits is developed. The maximum overlapping condition between consecutive applied patterns is identified. The application of the condition facilitated with the developed active sliding compatibility process significantly reduces the number of test clocks. It is demonstrated that the test clocks can be reduced by 50% on average from given test sets. Further evaluation shows that, for parity scan, the test clocks required by the authors' method are only 41% of those elsewhere View full abstract»

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  • One-dimensional processor arrays for linear algebraic problems

    Publication Year: 1995 , Page(s): 1 - 4
    Cited by:  Papers (2)  |  Patents (7)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (228 KB)  

    Using isomorphic embedding of the original dependence graphs in another graph before its space-time mapping onto array architectures, two linear processor arrays are designed for the Gauss-Jordan algorithm with partial pivoting and Cholesky decomposition. Each of these arrays comprises only (n+1)/2 processing elements (PEs), where n is the number of columns in the input matrices. The block pipelining period is n(n-1) cycles for the first array and n(n+1)/2 cycles for the second. If the matrices are processed sequentially, systems of linear equations are solved by the Gauss-Jordan algorithm with almost full processor utilisation, whereas for the Cholesky decomposition the utilisation of PEs is approximately two-thirds View full abstract»

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  • Using a resource-limited instruction scheduler to evaluate the iHARP processor

    Publication Year: 1995 , Page(s): 23 - 31
    Cited by:  Papers (4)  |  Patents (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (656 KB)  

    RISC processors have approached an execution rate of one instruction per cycle by using pipelining to speed up execution. However, to achieve an execution rate of more than one instruction per cycle, processors must issue multiple instructions in each processor cycle. The paper evaluates the architectural features of iHARP, a VLIW processor with an instruction issue rate of four, which has been developed at the University of Hertfordshire. A distinctive feature of iHARP is the provision of Boolean guards on all instructions. Instructions are then only executed at run time if the attached Boolean guard is true. A second distinctive feature is the use of an ORed indexing addressing mechanism to avoid load delays. The paper evaluates the benefits of both these features and quantifies their performance advantage. Other architectural features evaluated include instruction issue rate, code size, number of data cache ports, number of register file write ports, number of branch units, instruction combining and loop unrolling. The evaluation uses a resource-limited instruction scheduler, specifically developed to re-order code at compile times for parallel execution on iHARP View full abstract»

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