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IEEE Design & Test of Computers

Issue 1 • Date Spring 1995

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Displaying Results 1 - 7 of 7
  • System partitioning of MCMs for low power

    Publication Year: 1995, Page(s):41 - 52
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (788 KB)

    Meeting the design challenges inherent in complex multichip modules that also reduce power dissipation is a daunting task, considering the number of constraints and the nonlinear cost functions explored early in the prototyping process. Current algorithms do not do the job. A new systematic approach combines commercial software with simple size-reduction and linearization methods that are largely ... View full abstract»

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  • Automatic verification of asynchronous circuits

    Publication Year: 1995, Page(s):24 - 31
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    Verifying asynchronous designs is difficult, since design errors may manifest themselves only under rare circumstances. This article describes how to model asynchronous designs as programs in synchronized transitions, a general-purpose hardware description language. The authors show how this representation facilitates rigorous, efficient verification View full abstract»

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  • Specification and design of embedded hardware-software systems

    Publication Year: 1995, Page(s):53 - 67
    Cited by:  Papers (80)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1328 KB)

    Embedded-system specification and design consists of describing a system's desired functionality and mapping that functionality for implementation by a set of system components such as processors, ASICs, memories, and buses. This paper discusses the key problems of system specification and design, including specification capture, design exploration, hierarchical modeling, software and hardware syn... View full abstract»

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  • Designing self-timed devices using the finite automaton model

    Publication Year: 1995, Page(s):14 - 23
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (772 KB)

    The authors suggest a procedure for designing a self-timed device defined by the finite automaton model. This procedure proves useful when designing these devices using the available synchronous behavior specifications. They illustrate the effectiveness of their procedure by applying it to the design of a stack memory and constant acknowledgement delay counter View full abstract»

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  • High-level modeling and design of asynchronous interface logic

    Publication Year: 1995, Page(s):32 - 40
    Cited by:  Papers (15)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    The authors' new methodology uses formal models of concurrency to synthesize speed-independent circuit implementations from high-level, abstract behavioral specifications. This methodology offers the advantages of preserving behavioral semantics and better control flow abstraction. It also provides heuristics at a higher level of abstraction to help solve the complete state-coding problem View full abstract»

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  • Reducing hardware with fuzzy multiple signature analysis

    Publication Year: 1995, Page(s):68 - 74
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    Fuzzy multiple signature analysis seeks the middle ground between the complex implementation and high overhead of conventional multiple signature analysis and the less-desirable error detection rates of single signature analysis. This scheme relaxes the restriction of one-to-one reference-signature correspondence required by the conventional multiple signature scheme, yet retains significant fault... View full abstract»

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  • Managing your EDA investments

    Publication Year: 1995, Page(s):5 - 7, 89-90
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    Every IC/systems design manager faces the same optimization problem: how to minimize costs while maximizing productivity? Take it one or two organizational levels higher and the problem becomes even move critical. That's because individual performance ratings and bonuses are based on metrics such as below-budget, on-time delivery for new products. The following concepts are discussed: competitive ... View full abstract»

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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Editor-in-Chief
Krishnendu Chakrabarty