IEEE Design & Test

Issue 5 • Oct. 2017

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  • Front Cover

    Publication Year: 2017, Page(s): C1
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  • Cover 2

    Publication Year: 2017, Page(s): C2
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  • IEEE Design&Test publication information

    Publication Year: 2017, Page(s): 1
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  • Table of Contents

    Publication Year: 2017, Page(s):2 - 3
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  • Verification and Test

    Publication Year: 2017, Page(s): 4
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  • Guest Editors’ Introduction: Emerging Challenges and Solutions in SoC Verification

    Publication Year: 2017, Page(s):5 - 6
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  • Challenges and Trends in Modern SoC Design Verification

    Publication Year: 2017, Page(s):7 - 22
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB) | HTML iconHTML

    This paper provides a tutorial overview of the state-of-the-art in verification of complex and heterogeneous Systems-on-Chip. The authors discuss current industrial trends and key research challenges. View full abstract»

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  • Data-Driven Test Plan Augmentation for Platform Verification

    Publication Year: 2017, Page(s):23 - 29
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    This article points out that the fundamental problem of platform verification is incompleteness of the test plan and proposes an unsupervised learning approach to augment the test plan.-Magdy Abadir, Helic Inc. View full abstract»

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  • Formally Verifying Transfer Functions of Linear Analog Circuits

    Publication Year: 2017, Page(s):30 - 37
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    This article presents an approach to extend mathematical formal analysis towards verification of linear analog circuits. View full abstract»

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  • Embedded Systems Secure Path Verification at the Hardware/Software Interface

    Publication Year: 2017, Page(s):38 - 46
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (146 KB) | HTML iconHTML

    The article presents a case study comparing two types of properties for formal verification of security requirements in embedded systems. View full abstract»

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  • Leveraging Software Configuration Management in Automated RTL Design Debug

    Publication Year: 2017, Page(s):47 - 53
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    This article presents an enhancement to the existing automated debugging software by leveraging statistics from the revision control history. View full abstract»

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  • Formal-Based Design and Verification of SoC Arbitration Protocols: A Comparative Analysis of TDMA and Round-Robin

    Publication Year: 2017, Page(s):54 - 62
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1493 KB) | HTML iconHTML

    As System-On-Chips (SoCs) Are increasing in size and complexity, their validation and verification have become important and more difficult to achieve. Currently, the most widely used SoC design is typically bus based and consists of shared communication resources managed by dedicated arbiters that are in charge of serializing access requests. That is why the communication architecture as well as ... View full abstract»

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  • Probing Attacks on Integrated Circuits: Challenges and Research Opportunities

    Publication Year: 2017, Page(s):63 - 71
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (861 KB) | HTML iconHTML

    As a type of invasive physical attacks, probing attacks are able to access and directly monitor security critical nets of an IC and extract sensitive information. In this paper, the authors summarize the state-of-the-art probing and anti-probing technologies and their challenges, and discuss the opportunities in the relevant research. View full abstract»

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  • Tackling Test Challenges for Interposer-Based 2.5-D Integrated Circuits

    Publication Year: 2017, Page(s):72 - 79
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (745 KB) | HTML iconHTML

    2.5-D integrated circuit (IC) is a cost-efficient alternative to through-silicon-via (TSV)-based 3-D IC. In this paper, the authors give a comprehensive summary of the testing challenges of 2.5-D ICs and their existing solutions. They then present a test architecture using e-fuses for prebond interposer testing and a method to reduce power-supply noise during the testing. View full abstract»

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  • Will Chips of the Future Learn How to Feel Pain and Cure Themselves?

    Publication Year: 2017, Page(s):80 - 87
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (663 KB) | HTML iconHTML

    Extended transistor scaling has brought us a lot of benefits, but also a myriad of problems, including severe reliability issues [1]. To extend the scaling path as far as possible, system architects and technologists have to work together. They have to find solutions—e.g., at system level—to realize self-healing chips, chips that can detect or ... View full abstract»

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  • Call for Contributions Special Issue on Architecture Advances Enabled by Emerging Technologies

    Publication Year: 2017, Page(s):88 - 89
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  • An Interview With Professor Chenming Hu, Father of 3D Transistors

    Publication Year: 2017, Page(s):90 - 96
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  • Engineering Secure Internet of Things Systems

    Publication Year: 2017, Page(s):97 - 98
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  • IEEE Rebooting Computing Week

    Publication Year: 2017, Page(s):99 - 100
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  • Test Technology TC Newsletter

    Publication Year: 2017, Page(s):101 - 102
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  • Corrections

    Publication Year: 2017, Page(s): 103
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  • To Verification Infinity and Beyond

    Publication Year: 2017, Page(s): 104
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  • Cover 3

    Publication Year: 2017, Page(s): C3
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  • Cover 4

    Publication Year: 2017, Page(s): C4
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Aims & Scope

IEEE Design & Test offers original works describing the models, methods and tools used to design and test microelectronic systems from devices and circuits to complete systems-on-chip and embedded software. The magazine focuses on current and near-future practice, and includes tutorials, how-to articles, and real-world case studies. The magazine seeks to bring to its readers not only important technology advances but also technology leaders, their perspectives through its columns, interviews and roundtable discussions. Topics include semiconductor IC design, semiconductor intellectual property blocks, design, verification and test technology, design for manufacturing and yield, embedded software and systems, low-power and energy efficient design, electronic design automation tools, practical technology, and standards.  

It was published as IEEE Design & Test of Computers between 1984 and 2012.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Joerg Henkel
Chair for Embedded Systems (CES)
Karlsruhe Institute of Technology (KIT)