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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 9 • Sept. 2017

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Displaying Results 1 - 19 of 19
  • Table of contents

    Publication Year: 2017, Page(s): C1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2017, Page(s): C2
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  • Design Automation of Cyber-Physical Systems: Challenges, Advances, and Opportunities

    Publication Year: 2017, Page(s):1421 - 1434
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1354 KB) | HTML iconHTML

    A cyber-physical system (CPS) is an integration of computation with physical processes whose behavior is defined by both computational and physical parts of the system. In this paper, we present a view of the challenges and opportunities for design automation of CPS. We identify a combination of characteristics that define the challenges unique to the design automation of CPS. We then present sele... View full abstract»

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  • Hiding Hardware Trojan Communication Channels in Partially Specified SoC Bus Functionality

    Publication Year: 2017, Page(s):1435 - 1444
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1314 KB) | HTML iconHTML

    On-chip bus implementations must be bug-free and secure to provide the functionality and performance required by modern system-on-a-chip (SoC) designs. Regardless of the specific topology and protocol, bus behavior is never fully specified, meaning there exist cycles/conditions where some bus signals are irrelevant, and ignored by the verification effort. We highlight the susceptibility of current... View full abstract»

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  • PUF-Based Fuzzy Authentication Without Error Correcting Codes

    Publication Year: 2017, Page(s):1445 - 1457
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2882 KB) | HTML iconHTML

    Counterfeit integrated circuits (IC) can be very harmful to the security and reliability of critical applications. Physical unclonable functions (PUFs) have been proposed as a mechanism for uniquely identifying ICs and thus reducing the prevalence of counterfeits. However, maintaining large databases of PUF challenge response pairs (CRPs) and dealing with PUF errors make it difficult to use PUFs r... View full abstract»

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  • Segment and Conflict Aware Page Allocation and Migration in DRAM-PCM Hybrid Main Memory

    Publication Year: 2017, Page(s):1458 - 1470
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2994 KB) | HTML iconHTML

    Phase change memory (PCM), given its nonvolatility, potential high density, and low standby power, is a promising candidate to be used as main memory in next generation computer systems. However, to hide its shortcomings of limited endurance and slow write performance, state-of-the-art solutions tend to construct a dynamic RAM (DRAM)-PCM hybrid memory and place write-intensive pages in DRAM. While... View full abstract»

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  • Multipumping Flexible DSP Blocks for Resource Reduction on Xilinx FPGAs

    Publication Year: 2017, Page(s):1471 - 1482
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1292 KB) | HTML iconHTML

    For complex datapaths, resource sharing can help reduce area consumption. Traditionally, resource sharing is applied when the same resource can be scheduled for different uses in different cycles, often resulting in a longer schedule. Multipumping is a method whereby a resource is clocked at a frequency that is a multiple of the surrounding circuit, thereby offering multiple executions per global ... View full abstract»

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  • Transistor Count Optimization in IG FinFET Network Design

    Publication Year: 2017, Page(s):1483 - 1496
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2547 KB) | HTML iconHTML

    Double-gate devices, like independent-gate (IG) FinFET, have introduced new possibilities and challenges in synthesis of transistor networks. Existing factorization methods and graph-based optimizations are not actually the most effective way to generate optimized IG FinFET based networks because only reducing the number of literals in a given Boolean expression does not guarantee the minimum tran... View full abstract»

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  • System-Level Effects of Soft Errors in Uncore Components

    Publication Year: 2017, Page(s):1497 - 1510
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1961 KB) | HTML iconHTML

    The effects of soft errors in processor cores have been widely studied. However, little has been published about soft errors in uncore components, such as the memory subsystem and I/O controllers, of a system-on-a-chip (SoC). In this paper, we study how soft errors in uncore components affect system-level behaviors. We have created a new mixed-mode simulation platform that combines simulators at t... View full abstract»

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  • Improved Perturbation Vector Generation Method for Accurate SRAM Yield Estimation

    Publication Year: 2017, Page(s):1511 - 1521
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2936 KB) | HTML iconHTML

    Accurate yield estimation under parametric variation is one of the most integral parts for robust and nonwasted circuit design. In particular, due to the significant impact of disparity on the high-replication circuit, precise yield estimation is essential in SRAM design. In this paper, we propose an enhanced perturbation vector generation method to improve the accuracy of the yield estimation of ... View full abstract»

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  • Fast Verification of Guide-Patterns for Directed Self-Assembly Lithography

    Publication Year: 2017, Page(s):1522 - 1531
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2189 KB) | HTML iconHTML

    Guide-patterns (GPs) are critical to the construction of contacts and vias in directed self-assembly (DSA) lithography. Simulations can be used to verify GPs, but runtime is excessive. Instead, we categorize the shapes of GPs using a small number of geometric parameters. Then a verification function is built to predict whether a GP will produce the required contacts, as follows: a vector in parame... View full abstract»

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  • High Performance Dummy Fill Insertion With Coupling and Uniformity Constraints

    Publication Year: 2017, Page(s):1532 - 1544
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1480 KB) | HTML iconHTML

    In deep-submicron very large scale integration manufacturing, dummy fills are widely applied to reduce topographic variations and improve layout pattern uniformity. However, the introduction of dummy fills may impact the wire electrical properties, such as coupling capacitance. Traditional tile-based method for fill insertion usually results in very large number of fills, which increases the cost ... View full abstract»

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  • Improved Tangent Space-Based Distance Metric for Lithographic Hotspot Classification

    Publication Year: 2017, Page(s):1545 - 1556
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1525 KB) | HTML iconHTML

    A distance metric of patterns is crucial to hotspot cluster analysis and classification. In this paper, we propose an improved tangent space (ITS)-based distance metric for hotspot cluster analysis and classification. The proposed distance metric is an important extension of the well-developed tangent space method in computer vision. It can handle patterns containing multiple polygons, while the t... View full abstract»

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  • WARM: Workload-Aware Reliability Management in Linux/Android

    Publication Year: 2017, Page(s):1557 - 1570
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1779 KB) | HTML iconHTML

    With CMOS scaling beyond 14 nm, reliability is a major concern for IC manufacturers. Reliability-aware design has a non-negligible overhead and cannot account for user experience in mobile devices. An alternative is dynamic reliability management (DRM), which counteracts degradation by adapting the operating conditions at runtime. In this paper, for the first time we formulate DRM as an optimizati... View full abstract»

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  • Enhancing Test Compression With Dependency Analysis for Multiple Expansion Ratios

    Publication Year: 2017, Page(s):1571 - 1579
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2013 KB) | HTML iconHTML

    Scan test data compression is widely used in industry to reduce test data volume (TDV) and test application time (TAT). This paper shows how multiple scan chain expansion ratios can help to obtain high test data compression in system-on-chips. Scan chains are partitioned with a higher expansion ratio than normal in scan compression mode and then are gradually concatenated based on a cost function ... View full abstract»

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  • Exploiting Unused Spare Columns and Replaced Columns to Enhance Memory ECC

    Publication Year: 2017, Page(s):1580 - 1591
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2302 KB) | HTML iconHTML

    Due to the emergence of extremely high density memory along with the growing number of embedded memories, memory yield is an important issue. Memory self-repair using redundancies to increase the yield of memories is widely used. Because high density memories are vulnerable to soft errors, memory error correction code (ECC) plays an important role in memory design. In this paper, methods to exploi... View full abstract»

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  • Introducing IEEE Collabratec

    Publication Year: 2017, Page(s): 1592
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2017, Page(s): C3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors

    Publication Year: 2017, Page(s): C4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu