# IEEE Transactions on Electron Devices

## Issue 9 • Sept. 2017

The purchase and pricing options for this item are unavailable. Select items are only available as part of a subscription package. You may try again later or contact us for more information.

## Filter Results

Displaying Results 1 - 25 of 72

Publication Year: 2017, Page(s):C1 - 3527
| |PDF (253 KB)
• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2017, Page(s): C2
| |PDF (71 KB)
• ### Improvements of Interfacial and Electrical Properties for Ge MOS Capacitor by Using TaYON Interfacial Passivation Layer and Fluorine Incorporation

Publication Year: 2017, Page(s):3528 - 3533
| |PDF (2167 KB) | HTML

Ge metal-oxide-semiconductor capacitor with HfTiON/TaYON stacked gate dielectric treated by fluorine plasma is fabricated, and its interfacial and electrical properties are compared with its counterparts without the TaYON interfacial passivation layer or the fluorine-plasma treatment. Experimental results show that the sample exhibits excellent performances: low interface-state density (2.5 ... View full abstract»

• ### A Threshold Voltage Model of Tri-Gate Junctionless Field-Effect Transistors Including Substrate Bias Effects

Publication Year: 2017, Page(s):3534 - 3540
| |PDF (1778 KB) | HTML

In this paper, the influence of substrate bias voltage and substrate-induced surface potential (SISP) on threshold voltage of tri-gate junctionless field-effect transistors (TG-JLFETs) has been investigated. For this purpose, a quasi-3-D threshold voltage model of TG-JLFETs is presented considering the effects of both back-bias voltage and a lightly doped substrate. To incorporate the effect of SI... View full abstract»

• ### Influence of Drain Doping Engineering on the Ambipolar Conduction and High-Frequency Performance of TFETs

Publication Year: 2017, Page(s):3541 - 3547
| |PDF (1592 KB) | HTML

In this paper, the effect of a proposed drain doping engineering on the ambipolar conduction and high-frequency performance of tunneling FETs (TFETs) is investigated using 2-D TCAD simulations. The proposed TFET structure is based on using a high-doped region above a low-doped region of the drain side. It is demonstrated that when splitting the drain into two regions, one with high doping above th... View full abstract»

• ### DC-30 GHz DPDT Switch Matrix Design in High Resistivity Trap-Rich SOI

Publication Year: 2017, Page(s):3548 - 3554
Cited by:  Papers (2)
| |PDF (2018 KB) | HTML

This paper presents low insertion loss, high isolation, ultra-wideband double-pole-double-throw (DPDT) switch matrix designed in a 0.13-μm commercial high resistivity trap-rich silicon-on-insulator (SOI) CMOS process for the first time. The switches are designed using series-shunt-series configuration in a ring-type structure with input and output matching networks. Transistor width and tra... View full abstract»

• ### A Predictive Model for IC Self-Heating Based on Effective Medium and Image Charge Theories and Its Implications for Interconnect and Transistor Reliability

Publication Year: 2017, Page(s):3555 - 3562
| |PDF (1435 KB) | HTML

Spatially resolved precise prediction of local temperature T(x,y,z) is essential to evaluate Arrhenius-activated interconnect (e.g., electromigration) and transistor reliability (e.g., NBTI, HCI, and TDDB). A 3-D finite-element modeling (FEM) do provide excellent results, but the calculation is too time-consuming for a structure that involves eight to ten layers of percolating interconnects, espec... View full abstract»

• ### Improving the Electrical Performance of a Quantum Well FET With a Shell Doping Profile by Heterojunction Optimization

Publication Year: 2017, Page(s):3563 - 3568
| |PDF (1441 KB) | HTML

This paper investigates the impacts of typical semiconductor material properties-electron affinity, bandgap, and dielectric constant, on the electrical performance of a p-type core-shell heterojunction nanowire FET by numerical simulations. At the heterojunction, a valence band offset of 200 meV forms a sufficient energy barrier confining the holes in the quantum well, resulting in the optimal OFF... View full abstract»

• ### Low-Leakage ESD Power Clamp Design With Adjustable Triggering Voltage for Nanoscale Applications

Publication Year: 2017, Page(s):3569 - 3575
| |PDF (2810 KB) | HTML

A low-leakage electrostatic discharge power clamp with adjustable triggering voltage (Vt1) is proposed in this paper. By enabling the static detection path using the transient one, the proposed clamp achieves a wide range of adjustable Vt1 while maintaining low standby leakage current (Ileak), which overcomes the flaw of traditional static clamps. Besides, the adju... View full abstract»

• ### Compact Modeling Source-to-Drain Tunneling in Sub-10-nm GAA FinFET With Industry Standard Model

Publication Year: 2017, Page(s):3576 - 3581
| |PDF (1450 KB) | HTML

We present a compact model for source-to-drain tunneling current in sub-10-nm gate-all-around FinFET, where tunneling current becomes nonnegligible. Wentzel-Kramers-Brillouin method with a quadratic potential energy profile is used to analytically capture the dependence on biases in the tunneling probability expression and simplify the equation. The calculated tunneling probability increases with ... View full abstract»

• ### Steep-Switching Germanium Junctionless MOSFET With Reduced OFF-State Tunneling

Publication Year: 2017, Page(s):3582 - 3587
| |PDF (1258 KB) | HTML

In this paper, we report on the reduction of the off-state band-to-band tunneling (BTBT) while maintaining sub-60 mV/decade switching in Germanium (Ge) Junctionless (JL) transistor through well-calibrated simulations. Recognizing the product of current density (J) and electric field (E) to be the key generic parameter governing device optimization, it is shown that a device with thicker film opera... View full abstract»

• ### SiC BJT Compact DC Model With Continuous- Temperature Scalability From 300 to 773 K

Publication Year: 2017, Page(s):3588 - 3594
| |PDF (2775 KB) | HTML

The first vertical bipolar intercompany (VBIC)-based compact dc model has been developed and verified for a low-voltage 4H-SiC bipolar junction transistor to continuously map a wide temperature range from 300 to 773 K. Temperature and doping dependent physical models for bandgap, incomplete ionization, carrier mobility, and lifetime have been taken into account to give physically meaningful fittin... View full abstract»

• ### The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs

Publication Year: 2017, Page(s):3595 - 3600
| |PDF (1890 KB) | HTML

The basic analog parameters of three splits of InxGa1-xAs nTFETs are analyzed for the first time. The first two splits are In0.53Ga0.47As devices with a 3-nm HfO2/1-nm Al2O3 and a 2-nm HfO2/1-nm Al2O3, while the last one is an In0.7Ga0.3As channel with a 3-nm HfO... View full abstract»

• ### Fabrication of InGaAs-on-Insulator Substrates Using Direct Wafer-Bonding and Epitaxial Lift-Off Techniques

Publication Year: 2017, Page(s):3601 - 3608
| |PDF (3476 KB) | HTML

Defect less semiconductor-on-insulator (-OI) by a cost-effective and low-temperature process is strongly needed for monolithic 3-D integration. Toward this, in this paper, we present a cost-effective fabrication of the indium gallium arsenide-OI structure featuring the direct wafer bonding (DWB) and epitaxial lift-off (ELO) techniques as well as the reuse of the indium phosphide donor wafer. We sy... View full abstract»

• ### Gate Leakage Mechanisms in AlInN/GaN and AlGaN/GaN MIS-HEMTs and Its Modeling

Publication Year: 2017, Page(s):3609 - 3615
| |PDF (3178 KB) | HTML

Gate leakage mechanisms in AlInN/GaN and AlGaN/GaN metal insulator semiconductor high-electron-mobility transistors (MIS-HEMTs) with SiNx as gate dielectric have been investigated. It is found that the conduction in the reverse gate bias is due to Poole-Frenkel emission for both MIS-HEMTs. The dominant conduction mechanism in low to medium forward bias is trap-assisted tunneling while i... View full abstract»

• ### Evidence of Time-Dependent Vertical Breakdown in GaN-on-Si HEMTs

Publication Year: 2017, Page(s):3616 - 3621
| |PDF (2056 KB) | HTML

This paper demonstrates and investigates the time-dependent vertical breakdown of GaN-on-Si power transistors. The study is based on electrical characterization, dc stress tests and electroluminescence measurements. We demonstrate the following original results: 1) when submitted to two-terminal (drain-to-substrate) stress, the AlGaN/GaN transistors show a time-dependent degradation process, which... View full abstract»

• ### Calibration of Bulk Trap-Assisted Tunneling and Shockley–Read–Hall Currents and Impact on InGaAs Tunnel-FETs

Publication Year: 2017, Page(s):3622 - 3626
| |PDF (1233 KB) | HTML

The tunnel-FET (TFET) is a promising candidate for future low-power logic applications, because it enables a sub-60-mV/decadesubthresholdswing. However, themost experimental TFETs are plagued by unwanted trap-assisted tunneling (TAT) and Shockley-Read-Hall (SRH) carrier generation, which degrade the swing and increase the leakage floor, hence forming a major roadblock for TFET adoption. This degra... View full abstract»

• ### High-Power ${X}$ -Band 5-b GaN Phase Shifter With Monolithic Integrated E/D HEMTs Control Logic

Publication Year: 2017, Page(s):3627 - 3633
| |PDF (3245 KB) | HTML

A high-power X-band GaN-based 5-b digital phase shifter with control logic circuit on-chip is demonstrated for the first time, which is implemented with monolithic integrated GaN E/D HEMTs fabrication process. Gate trench etching together with Al2O3 as gate dielectric is used to form the gate of the E-mode GaN HEMTs. Switched filter and high-pass/low-pass topology are used to design the 11.25�... View full abstract»

• ### Comparison for 1/ ${f}$ Noise Characteristics of AlGaN/GaN FinFET and Planar MISHFET

Publication Year: 2017, Page(s):3634 - 3638
| |PDF (1497 KB) | HTML

DC and 1/f noise performances of the AlGaN/GaN fin-shaped field-effect transistor (FinFET) with fin width of 50 nm were analyzed. The FinFET exhibited approximately six times larger normalized drain current and transconductance, compared to those of the AlGaN/GaN planar metal-insulator-semiconductor heterostructure field-effect-transistor (MISHFET) fabricated on the same wafer. It was also observe... View full abstract»

• ### A Study on Practically Unlimited Endurance of STT-MRAM

Publication Year: 2017, Page(s):3639 - 3646
| |PDF (1856 KB) | HTML

Magnetic tunnel junctions integrated for spin-transfer torque magnetoresistive random-access memory are by far the only known solid-state memory element that can realize a combination of fast read/write speed and high endurance. This paper presents a comprehensive validation of high endurance of deeply scaled perpendicular magnetic tunnel junctions (pMTJs) in light of various potential spin-transf... View full abstract»

• ### Fully Coupled Multiphysics Simulation of Crosstalk Effect in Bipolar Resistive Random Access Memory

Publication Year: 2017, Page(s):3647 - 3653
| |PDF (3075 KB) | HTML

A versatile multiphysics simulation packet for investigating different resistive random acces memories (RRAMs) is developed in this paper. Heat transfer, electrical conduction, and ion migration in such heterogeneous structure are all taken into consideration. Three fully coupled partial differential equations are solved using our self-developed finite-difference algorithm, where Scharfetter-Gumme... View full abstract»

• ### Analytical Drain Current Model for Amorphous InGaZnO Thin-Film Transistors at Different Temperatures Considering Both Deep and Tail Trap States

Publication Year: 2017, Page(s):3654 - 3660
| |PDF (2959 KB) | HTML

Surface-potential-based drain current model is presented for amorphous InGaZnO thin-film transistors considering both exponential deep and tail trap states densities in the energy gap. The trap states densities are determined by the numerical calculation on the basis of the assumption that the trapped carrier concentration is much higher than the free carrier concentration. The analytical drain cu... View full abstract»

• ### Analytical Model for 2DEG Density in Graded MgZnO/ZnO Heterostructures With Cap Layer

Publication Year: 2017, Page(s):3661 - 3667
| |PDF (1424 KB) | HTML

In this paper, we develop a generic analytical model for 2-D electron gas (2DEG) density (ns) and threshold voltage (VOFF) of a fully strained graded ZnO-based heterostructure with a cap layer. The model is based on the continuity of electric field at the interfaces of different layers, dominant piezoelectric and spontaneous polarization components in different layers, Mg com... View full abstract»

• ### Integrating Poly-Silicon and InGaZnO Thin-Film Transistors for CMOS Inverters

Publication Year: 2017, Page(s):3668 - 3671
| |PDF (1317 KB) | HTML

The applications of a-InGaZnO thin-film transistors (TFTs) to logic circuits have been limited owing to the intrinsic n-channel operation. In this paper, we demonstrated a hybrid inverter constructed by p-channel low-temperature poly-silicon (LTPS) TFTs and n-channel amorphous-indium-gallium-zinc-oxide (a-IGZO) TFTs. Hydrogenated LTPS TFTs and a-IGZO TFTs have been successfully fabricated on the s... View full abstract»

• ### Light Extraction Enhancement of GaN-Based Light-Emitting Diodes With Textured Sidewalls and ICP-Transferred Nanohemispherical Backside Reflector

Publication Year: 2017, Page(s):3672 - 3677
| |PDF (2765 KB) | HTML

Textured-sidewall GaN-based light-emitting diodes (LEDs) with convex and 45° patterns and an inductively coupled plasma (ICP)-transferred nanohemispherical backside reflector, formed using an ICP etching process, are fabricated and studied. For devices with textured sidewalls, the scattering probability of photons at the GaN/air interface is increased and the light extraction efficiency is ... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy