# IEEE Transactions on Electron Devices

## Issue 8 • Aug. 2017

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## Filter Results

Displaying Results 1 - 25 of 77

Publication Year: 2017, Page(s):C1 - 3043
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• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2017, Page(s): C2
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• ### Electrostatic Doping in Semiconductor Devices

Publication Year: 2017, Page(s):3044 - 3055
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To overcome the limitations of chemical doping in nanometer-scale semiconductor devices, electrostatic doping (ED) is emerging as a broadly investigated alternative to provide regions with a high electron or hole density in a semiconductor device. In this paper, we review various reported ED approaches and related device architectures in different material systems. We highlight the role of metal a... View full abstract»

• ### Analytical Modeling of DG-MOSFET in Subthreshold Regime by Green’s Function Approach

Publication Year: 2017, Page(s):3056 - 3062
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In this paper, we have developed an analytical model of double gate MOSFET using Green's function approach in the subthreshold regime of operation. The exact analytical solution to 2-D Poisson's equation by Green's function approach is redefined and Fourier coefficients are calculated correctly that has a direct impact on the outcomes of the model. The approach considers 2-D mixed boundary conditi... View full abstract»

• ### Impact of Gate/Spacer-Channel Underlap, Gate Oxide EOT, and Scaling on the Device Characteristics of a DG-RFET

Publication Year: 2017, Page(s):3063 - 3070
Cited by:  Papers (1)
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A reconfigurable field-effect transistor (RFET) with the ability to provide both n- and p-type characteristics with a single transistor is among the class of those emerging devices which show great promise to become the building block of future nanoelectronics. A comprehensive investigation using extensive 3-D device simulations on the effects of varying the gate-channel and spacer-channel underla... View full abstract»

• ### Analytical Estimation of Threshold Voltage Variability by Metal Gate Granularity in FinFET

Publication Year: 2017, Page(s):3071 - 3076
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Metal gate granularity (MGG)-induced threshold voltage variability is the dominant source of variability in FinFETs. The analytical model for MGG-based variability is essential to study its circuit impact. In this paper, we present a novel electrostatics and percolation theory-based analytical model to estimate MGG-induced threshold voltage (VT) variability. The model is capable of analyzing reali... View full abstract»

• ### Localized Tunneling Phenomena of Nanometer Scaled High- ${K}$ Gate-Stack

Publication Year: 2017, Page(s):3077 - 3083
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The 3-D simulator, which is capable of sensing potential change due to single electron's movement via a local trap inside the high-K gate-stacking block, is developed. Then, we carefully investigate how the electron's movement effects on the reliabilities of high-K gate-stack far beyond 10-nm generations. The simulation result shows that the potential change caused by a single electron's charge is... View full abstract»

• ### Implementation of Band-to-Band Tunneling Phenomena in a Multisubband Ensemble Monte Carlo Simulator: Application to Silicon TFETs

Publication Year: 2017, Page(s):3084 - 3091
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Tunnel FETs (TFETs) are in the way to become an alternative to conventional MOSFETs due to the possibility of achieving low subthreshold swing combined with small OFF current levels, which allows operation at low VDD. In this paper, a nonlocal band-to-band tunneling model has been successfully implemented into a multisubband ensemble Monte Carlo (MS-EMC) simulator and applied to ultrasc... View full abstract»

• ### Device-Circuit Analysis of Ferroelectric FETs for Low-Power Logic

Publication Year: 2017, Page(s):3092 - 3100
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Ferroelectric FETs (FEFETs) are emerging devices with an immense potential to replace conventional MOSFETs by virtue of their steep switching characteristics. The ferroelectric (FE) material in the gate stack of the FEFET exhibits negative capacitance resulting in voltage step-up action which entails sub-60 mV/decade subthreshold swing at room temperature. The thickness of the FE layer (TFE View full abstract»

• ### Compact On-Wafer Test Structures for Device RF Characterization

Publication Year: 2017, Page(s):3101 - 3107
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The main objective of this paper is to validate the radio frequency (RF) characterization procedure based on compact test structures compatible with 50-μm-pitch RF probes. It is shown that by using these new test structures, the layout geometry and hence the on-chip space consumption for complete sets of passive and active devices, e.g., coplanar waveguide transmission lines and RF MOSFETs,... View full abstract»

• ### Impact of Traps and Strain on Optimized n- and p-Type TFETs Integrated on the Same InAs/AlGaSb Technology Platform

Publication Year: 2017, Page(s):3108 - 3113
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A simulation study on the impact of interface traps and strain on the I-V characteristics of co-optimized p- and n-type tunnel FETs (TFETs) realized on the same InAs/Al0.05Ga0.95Sb technology platform is carried out, using a full-quantum ballistic simulator. In order to capture the effect of interface/border traps on the device electrostatics consistently with carrier degener... View full abstract»

• ### Graded AlGaN Channel Transistors for Improved Current and Power Gain Linearity

Publication Year: 2017, Page(s):3114 - 3119
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We report on the small-signal high frequency characteristics of highly scaled graded AlGaN channel polarization-doped field-effect transistors (PolFETs) that show constant current gain cutoff frequency (fT) and maximum oscillation frequency (fmax) profiles as a function of current density or gate bias. The device design includes upward and downward Al composition grading to i... View full abstract»

• ### T-Shaped III-V Heterojunction Tunneling Field-Effect Transistor

Publication Year: 2017, Page(s):3120 - 3125
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In this paper, we propose and investigate a novel heterojunction T-shaped tunneling field-effect transistor (TTFET) using Sentaurus technology computer-aided design (TCAD) simulations. The electrical characteristics of InP/In0.53Ga0.47 As heterojunction TTFET are compared with an L-shaped tunneling field-effect transistor (LTFET) and are found to be superior. The proposed T-s... View full abstract»

• ### Instability of Dynamic- $R_{\text ON}$ and Threshold Voltage in GaN-on-GaN Vertical Field-Effect Transistors

Publication Year: 2017, Page(s):3126 - 3131
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This paper investigates the recoverable degradation of GaN-on-GaN vertical transistors under positive gate bias stress. Based on combined pulsed measurements and constant voltage stress test, we demonstrate the following original results: 1) when subjected to moderate gate stress (0 V <; VGS <; 3 V), the devices show a negative threshold voltage shift, which is correlated with a d... View full abstract»

• ### Time-Dependent Dielectric Breakdown in High-Voltage GaN MIS-HEMTs: The Role of Temperature

Publication Year: 2017, Page(s):3132 - 3138
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We have investigated time-dependent dielectric breakdown in high-voltage AlGaN/GaN metal-insulator-semiconductor high-electron mobility transistors, with a focus specifically on the role of temperature under positive gate stress conditions. We aim toward understanding the temperature dependence of progressive breakdown (PBD) as well as hard breakdown. We find that the temperature dependence of tim... View full abstract»

• ### Positive Shift in Threshold Voltage Induced by CuO and NiOx Gate in AlGaN/GaN HEMTs

Publication Year: 2017, Page(s):3139 - 3144
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AlGaN/GaN HEMTs with two kinds of p-type metal-oxide (CuO and NiOx) gates have been fabricated, in which the threshold voltage can be modulated effectively. Especially, the threshold voltage of the device shows a 0.7 V positive shift with a high-quality CuO gate layer. Meanwhile, a high on/off current ratio of ~109, a large saturated drain current of ~1030 mA/mm, and an improved transconductance o... View full abstract»

• ### Multifilamentary Conduction Modeling in Transition Metal Oxide-Based RRAM

Publication Year: 2017, Page(s):3145 - 3150
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Filamentary conduction paths through insulating solid electrolytes is a widely accepted theory describing the conduction phenomenon in resistive random access memories (RRAMs). In this work, the relationship between filamentary conduction and multilevel resistive states obtained as a result of VSTOP during the RESET process has been analyzed in detail to understand the underlying physics of resist... View full abstract»

• ### Low-Power Forming Free TiO2–x/HfO2–y/TiO2–x-Trilayer RRAM Devices Exhibiting Synaptic Property Characteristics

Publication Year: 2017, Page(s):3151 - 3158
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The insertion of an HfO2-y layer within TiO2-x/HfO2-y/TiO2-x resistive random access memory (RRAM) yields in low set power of 50 nW (10 nA at 5 V), low reset power of 3 nW (1 nA at -3 V), and good cycling variability (σ/μ <; 0.5). In addition, under pulse experiments, fast switching time of 1 μs, good 107 cycling endurance and ret... View full abstract»

• ### Resistive Switching with Self-Rectifying Tunability and Influence of the Oxide Layer Thickness in Ni/HfO2/n+-Si RRAM Devices

Publication Year: 2017, Page(s):3159 - 3166
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The impact of the dielectric thickness, forming polarity, and current compliance on the self-rectifying current-voltage(I-V) characteristics of Ni/HfO2/n+-Si resistive random access memory (RRAM) devices was investigated. The obtained results indicate that these three aspects not only play a role in the postforming currents but also affect the switching properties of the devi... View full abstract»

• ### Systematic Analysis of High-Current Effects in Flexible Polycrystalline-Silicon Transistors Fabricated on Polyimide

Publication Year: 2017, Page(s):3167 - 3173
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This paper systematically studies high-current-induced effects, hot-carrier effects, and self-heating effects in flexible low-temperature polycrystalline-silicon thin-film transistors fabricated on polyimide. By utilizing I-V and various-frequency C-V measurements, the exact location of defects generated by the self-heating effects can be clarified. The degradation mechanism is found to originate ... View full abstract»

• ### Investigation of High-Performance ITO-Stabilized ZnO TFTs With Hybrid-Phase Microstructural Channels

Publication Year: 2017, Page(s):3174 - 3182
Cited by:  Papers (1)
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In this paper, the properties of hybrid-phase microstructural indium tin oxide-stabilized ZnO thin films and the relevant high-performance thin-film transistors (TFTs) were systematically investigated. The optically extracted Urbach energy revealed that such thin films owned less band-tail state trapping in comparison with that of the corresponding amorphous thin films. This was determined by bett... View full abstract»

• ### Temperature-Dependent Electrical Characterization of Amorphous Indium Zinc Oxide Thin-Film Transistors

Publication Year: 2017, Page(s):3183 - 3188
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In this study, N-type amorphous indium zinc oxide thin-film transistors are fabricated and temperature-dependent electrical characteristics in the range of 170-295 K are analyzed through experimental measurements and using an equivalent-circuit model. In this model, thermionic field emission for reverse bias and a thermionic emission mechanism for forward bias are applied. The barrier height coeff... View full abstract»

• ### Electro-Thermal Annealing Method for Recovery of Cyclic Bending Stress in Flexible a-IGZO TFTs

Publication Year: 2017, Page(s):3189 - 3192
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Amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) fabricated by low-temperature processes on a flexible substrate can easily be degraded by mechanical deformation. Furthermore, lower performance in terms of the initial characteristics and reliability levels compared to those fabricated on glass substrates with relatively high heat treatments is inevitable. To solve these problems, a local... View full abstract»

• ### Hydrogenated Amorphous Silicon Gate Driver With Low Leakage for Thin-Film Transistor Liquid Crystal Display Applications

Publication Year: 2017, Page(s):3193 - 3198
| |PDF (1966 KB) | HTML

This paper presents a new low-leakage gate driver circuit using hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) for active-matrix liquid crystal display (AMLCD) applications. The pull-down TFTs are turned OFF to maintain the high driving capability of the proposed circuit. Four phase clock signals with a duty ratio of 33% are utilized to turn ON the pull-down TFTs in advance t... View full abstract»

• ### A 4-M Pixel High Dynamic Range, Low-Noise CMOS Image Sensor With Low-Power Counting ADC

Publication Year: 2017, Page(s):3199 - 3205
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In this paper, we present a 4-Mpixel high dynamic range (DR), low dark noise CMOS image sensor. The pixel design is based on a 4-T PPD structure, with one dedicated High Dynamic Range transistor added in serial with the reset transistor for changing the conversion factor during readout to enhance the DR. A low-power ramp counting Analog to Digital Convertor array is implemented to suppress the str... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy