# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

## Issue 7 • July 2017

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## Filter Results

Displaying Results 1 - 22 of 22

Publication Year: 2017, Page(s):C1 - C4
| |PDF (685 KB)
• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Publication Year: 2017, Page(s): C2
| |PDF (66 KB)
• ### A Variation-Tolerant Near-Threshold Processor With Instruction-Level Error Correction

Publication Year: 2017, Page(s):1993 - 2006
| |PDF (3188 KB) | HTML

Timing error resilience is a promising alternative to eliminate margins and improve energy efficiency in subthreshold and near-threshold processors. However, the existing techniques have some limitations, such as uncontaminated architecture registers (ARs), strict timing constraints on error consolidation and propagation, and high design complexity. To address these limitations, a new timing error... View full abstract»

• ### A Closed-Form Expression for Minimum Operating Voltage of CMOS D Flip-Flop

Publication Year: 2017, Page(s):2007 - 2016
| |PDF (2054 KB) | HTML

In this paper, a closed-form expression for estimating the minimum operating voltage (VDDmin) of D flip-flops (FFs) is proposed. VDDmin is defined as the minimum supply voltage at which the FFs are functional without errors. The proposed expression indicates that VDDmin of FFs is a linear function of the square root of logarithm of the number of FFs, and its slope ... View full abstract»

• ### Temperature-Aware Dynamic Voltage Scaling to Improve Energy Efficiency of Near-Threshold Computing

Publication Year: 2017, Page(s):2017 - 2026
| |PDF (1470 KB) | HTML

Power and energy reduction is of uttermost importance for applications with stringent power/energy budget such as ultralow power and energy-harvested systems. Aggressive voltage scaling and in particular near-threshold computing is a promising approach to reduce the power and energy consumption. However, reducing the supply voltage leads to drastic performance variation induced by process and runt... View full abstract»

• ### A Word Line Pulse Circuit Technique for Reliable Magnetoelectric Random Access Memory

Publication Year: 2017, Page(s):2027 - 2034
Cited by:  Papers (1)
| |PDF (4119 KB) | HTML

A word line pulse (WLP) circuit scheme is proposed toward the implementation of magnetoelectric random access memory (MeRAM). The circuit improves the write error rate (WER) and cell area efficiency by generating a better write pulse compared to conventional bitline pulse (BLP) techniques in terms of the pulse slew rate and amplitude. For the voltage-controlled magnetic anisotropy-induced precessi... View full abstract»

• ### IcoNoClast: Tackling Voltage Noise in the NoC Power Supply Through Flow-Control and Routing Algorithms

Publication Year: 2017, Page(s):2035 - 2044
| |PDF (3263 KB) | HTML

Power supply noise (PSN) is a growing concern in modern multiprocessor system-on-chips (MPSoCs). The advent of new architectures, such as the network-on-chip (NoC), the standard for on-chip communication in MPSoCs, has given rise to new challenges in maintaining reliable and energy-efficient operation. The growing NoC power footprint, increase in the transistor current, and high switching speed of... View full abstract»

• ### An ECC-Assisted Postpackage Repair Methodology in Main Memory Systems

Publication Year: 2017, Page(s):2045 - 2058
| |PDF (3214 KB) | HTML

As dynamic random access memories (DRAMs) operate in the field, hard errors resulting from wearout occur. Unless corrected or repaired, hard errors halt normal operations, degrading the performance of a system and causing the replacement of memory modules. To improve performance and availability of memory modules, error-correcting codes (ECCs) are employed in a memory system. However, since recent... View full abstract»

• ### Bridging Presilicon and Postsilicon Debugging by Instruction-Based Trace Signal Selection in Modern Processors

Publication Year: 2017, Page(s):2059 - 2070
| |PDF (2034 KB)

Although using presilicon information in postsilicon debugging phase seems interesting, space and time limitations of existing formal verification tools restrict the possibility of this idea. In this paper, the effective usage of presilicon information to enhance postsilicon trace signal selection in modern processors is discussed. Furthermore, a novel architecture for dynamic per-cycle selection ... View full abstract»

• ### A Cost-Effective Fault Tolerance Technique for Functional TSV in 3-D ICs

Publication Year: 2017, Page(s):2071 - 2080
| |PDF (4619 KB) | HTML

Regular and redundant through-silicon via (TSV) interconnects are used in fault tolerance techniques of 3-D IC. However, the fabrication process of TSVs results in defects that reduce the yield and reliability of TSVs. On the other hand, each TSV is associated with a significant amount of on-chip area overhead. Therefore, unlike the state-of-the-art fault tolerance architectures, here we propose t... View full abstract»

• ### Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System

Publication Year: 2017, Page(s):2081 - 2094
| |PDF (4752 KB) | HTML

A realistic assessment of optical networks-on-chip (ONoCs) can be performed only in the context of a comprehensive floorplanning strategy for the system as a whole, especially when the 3-D stacking of electronic and optical layers is implemented. This paper fosters layout-aware ONoC design by developing a physical mapping methodology for wavelength-routed ONoC topologies subject to the floorplanni... View full abstract»

• ### Maximizing Common Idle Time on Multicore Processors With Shared Memory

Publication Year: 2017, Page(s):2095 - 2108
| |PDF (4288 KB) | HTML

Nowadays, memory energy reduction attracts significant attention as main memory consumes large amount of energy among all the energy consuming components. This paper focuses on reducing the energy consumption of the shared main memory in multicore processors by putting the memory into sleep state when all cores are idle. Based on this idea, we present systematic analysis of different models and pr... View full abstract»

• ### Design Methodologies for Low-Power 3-D ICs With Advanced Tier Partitioning

Publication Year: 2017, Page(s):2109 - 2117
| |PDF (5501 KB) | HTML

Low power is considered as the driving force for 3-D ICs, yet there have been few thorough design studies on how to reduce power in 3-D ICs. In this paper, we discuss computer-aided design techniques and design methodologies to reduce power consumption in 3-D IC designs using a commercial grade CPU core (OpenSPARC T2 core). To demonstrate power benefits in 3-D ICs, four design techniques are explo... View full abstract»

• ### Impact and Design Guideline of Monolithic 3-D IC at the 7-nm Technology Node

Publication Year: 2017, Page(s):2118 - 2129
| |PDF (9743 KB) | HTML

Monolithic 3-D (M3D) IC is one of the potential technologies to break through the challenges of continued circuit power and performance scaling. In this paper, for the first time, we demonstrate the power benefits of M3D and present design guideline in a 7-nm FinFET technology node. The predictive 7-nm process design kit (PDK) and the standard cell library using both high-performance (HP) and low-... View full abstract»

• ### Adaptive In-Cache Streaming for Efficient Data Management

Publication Year: 2017, Page(s):2130 - 2143
| |PDF (2553 KB) | HTML

The design of adaptive architectures is frequently focused on the sole adaptation of the processing blocks, often neglecting the power/performance impact of data transfers and data indexing in the memory subsystem. In particular, conventional address-based models, supported on cache structures to mitigate the memory wall problem, often struggle when dealing with memory-bound applications or arbitr... View full abstract»

• ### Double Logarithmic Arithmetic Technique for Low-Power 3-D Graphics Applications

Publication Year: 2017, Page(s):2144 - 2152
| |PDF (2366 KB) | HTML

An energy efficient double logarithmic arithmetic (DLA) technique is proposed for 3-D graphics applications. DLA manipulates the logarithmic arithmetic and improves the architecture for the realization of the transcendental functions and the advanced lighting model using energy efficient techniques. The DLA features complete elimination of multipliers in logarithmic domain by using successive loga... View full abstract»

• ### CP-FPGA: Energy-Efficient Nonvolatile FPGA With Offline/Online Checkpointing Optimization

Publication Year: 2017, Page(s):2153 - 2163
| |PDF (4796 KB) | HTML

Field-programmable gate arrays (FPGAs) have drawn lots of attentions due to their programmability and high performance. Recently, ultralow-power FPGAs for Internet of Things, together with energy-harvesting technique, have become an emerging self-powered computing platform. However, volatile memory in FPGA will lose their states under unstable power supplies and cannot work efficiently. Nonvolatil... View full abstract»

• ### High-Current Drivability Fibonacci Charge Pump With Connect–Point–Shift Enhancement

Publication Year: 2017, Page(s):2164 - 2173
| |PDF (3459 KB) | HTML

A switched-capacitor dc-dc voltage regulator that converts an input of 2.4-3.6 V to an output of 30 V has been designed to power display driver integrated circuits. A novel Fibonacci structure, named connect-point-shift, is proposed to improve the current drivability, which increases the minimum current drivability from 0.16 to 0.274 mA. This scheme saves the chip size by approximately 40% while p... View full abstract»

• ### A Temperature Estimation Method Using the Ratio of Emitter-to-Base Voltages

Publication Year: 2017, Page(s):2174 - 2182
Cited by:  Papers (1)
| |PDF (2269 KB) | HTML

A temperature estimation method is proposed which utilizes the ratio of two emitter-to-base voltages of bipolar transistors. This removes the need for a precision reference voltage from the digitization step by implicitly implementing the reference in the digital backend. Using measurement data for p-n-p transistors in a 65-nm CMOS technology, we show that the proposed scheme is tolerant to tens o... View full abstract»

• ### Security-Adaptive Voltage Conversion as a Lightweight Countermeasure Against LPA Attacks

Publication Year: 2017, Page(s):2183 - 2187
Cited by:  Papers (3)
| |PDF (2579 KB) | HTML

A voltage converter with adaptive security features is proposed as a lightweight countermeasure against leakage power analysis (LPA) attacks. When an LPA attack is sensed by the proposed security-adaptive (SA) voltage converter, a discharging resistor starts sinking redundant current to alter the signature of the load power dissipation. The power dissipation induced by the discharging resistor is ... View full abstract»

• ### A Residue-to-Binary Converter for the Extended Four-Moduli Set ${2^{n}-1, 2^{n}+1, 2^{2n}+1, 2^{2n+p}}$

Publication Year: 2017, Page(s):2188 - 2192
| |PDF (590 KB)

This brief presents a residue-to-binary converter for the moduli set {2n - 1, 2n + 1, 22n + 1, 22n+p}, where n is a positive integer and 0 ≤ p ≤ n - 2. The converter consists of three simplified 4n-bit carry-save adders (CSAs) along with a modulo (24n -1) adder. The main contribution of this brief is reducing the requirements of ... View full abstract»

• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Publication Year: 2017, Page(s): C3
| |PDF (79 KB)

## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu