IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 7 • July 2017

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  • Table of contents

    Publication Year: 2017, Page(s): C1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2017, Page(s): C2
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  • ToPoliNano: A CAD Tool for Nano Magnetic Logic

    Publication Year: 2017, Page(s):1061 - 1074
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2445 KB) | HTML iconHTML

    In the post-CMOS scenario, field coupled nanotechnologies represent an innovative and interesting new direction for electronic nanocomputing. Among these technologies, nanomagnet logic (NML) makes it possible to finally embed logic and memory in the same device. To fully analyze the potential of NML circuits, design tools that mimic the CMOS design-flow should be used for circuit design. We presen... View full abstract»

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  • MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts

    Publication Year: 2017, Page(s):1075 - 1088
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2736 KB) | HTML iconHTML

    Self-aligned multiple patterning, due to its low overlay error, has emerged as the leading option for 1-D gridded back-end-of-line (BEOL) in sub-14-nm nodes. To form actual routing patterns from a uniform “sea of wires,” cut masks are needed for line-end cutting or realization of space between routing segments. The line-end cutting results in nonfunctional (i.e., dummy fill) patterns... View full abstract»

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  • TSF3D: MSV-Driven Power Optimization for Application-Specific 3D Network-on-Chip

    Publication Year: 2017, Page(s):1089 - 1102
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2068 KB) | HTML iconHTML

    Power consumption has become one of the major challenges in current chip design. One effective low power technology, multiple supply voltages (MSVs), has succeeded in 2D network-on-chip (NoC) design. However, few researches considered the MSV in 3D NoC, especially application-specific 3D NoC. In this paper, a complete three-stage synthesis flow for MSV-driven application-specific 3D NoC is propose... View full abstract»

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  • Minimum Implant Area-Aware Placement and Threshold Voltage Refinement

    Publication Year: 2017, Page(s):1103 - 1112
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1216 KB) | HTML iconHTML

    Threshold voltage assignment is a very effective technique to reduce leakage power consumption in modern integrated circuit design. As feature size continues to decrease, the layout constraints [called minimum implant area (MinIA) constraints] on the implant area, which determines the threshold voltage of a device, are becoming increasingly difficult to satisfy. It is necessary to take these const... View full abstract»

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  • Redundant Local-Loop Insertion for Unidirectional Routing

    Publication Year: 2017, Page(s):1113 - 1125
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1692 KB) | HTML iconHTML

    As the semiconductor manufacturing technology continues to scale down to sub-10 nm, unidirectional layout style has become the mainstream for lower metal layers with tight pitches. Conventional redundant via (RV) insertion for yield improvement has become obsolete because unidirectional routing patterns forbid off-track routing, i.e., wire bending, for the metal coverage of RVs. To enhance the yie... View full abstract»

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  • Incremental Layer Assignment Driven by an External Signoff Timing Engine

    Publication Year: 2017, Page(s):1126 - 1139
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2073 KB) | HTML iconHTML

    Modern technologies provide wide and thick metal layers that must be wisely used to reduce the delay of critical interconnections. After global routing, incremental layer assignment can improve the circuit timing by properly selecting critical interconnect segments to be routed in the faster (but very limited) wires on upper layers. Existing techniques based on net-by-net iterative improvement may... View full abstract»

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  • Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict

    Publication Year: 2017, Page(s):1140 - 1152
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2073 KB) | HTML iconHTML

    Triple patterning lithography (TPL) is one of the most promising lithography technology in sub-14-nm technology nodes, especially for complicated low metal layer manufacturing. To overcome the intracell routability problem and improve the cell regularity, recently middle-of-line (MOL) layers are employed in standard cell design. However, MOL layers may introduce a large amount of cross-row TPL con... View full abstract»

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  • A Design-Time Method for Building Cost-Effective Run-Time Power Monitoring

    Publication Year: 2017, Page(s):1153 - 1166
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3610 KB) | HTML iconHTML

    The emergence of power as a first-class design constraint has fueled the proposal of a growing number of optimization techniques, seeking the best tradeoff to reach the maximum energy efficiency. Effective adaptation strategies depend critically on the monitoring method as an incorrect assessment of the system's state will result in poor decision making. Yet it is indeed a fundamental issue: how t... View full abstract»

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  • FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency

    Publication Year: 2017, Page(s):1167 - 1180
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2435 KB) | HTML iconHTML

    Aggressive technology scaling and adoption of multilevel-cell technique lead to progressive increase of bit error rate (BER) of NAND flash memory. Consequently, conventional error correction code is not adequate to guarantee system reliability. As an alternative, low density parity check (LDPC) code is introduced to provide more powerful error correction capability. However, to achieve better perf... View full abstract»

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  • Persistent and Nonpersistent Error Optimization for STT-RAM Cell Design

    Publication Year: 2017, Page(s):1181 - 1192
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2006 KB) | HTML iconHTML

    Rapidly increasing demands for memory capacity and severe technical scaling challenges of conventional memory technologies motivated recent investments on next-generation nonvolatile memory technologies. As a promising candidate, spin-transfer torque random access memory (STT-RAM) has demonstrated many attractive properties, such as nanosecond access time, high integration density, nonvolatility, ... View full abstract»

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  • Transparent In-Circuit Assertions for FPGAs

    Publication Year: 2017, Page(s):1193 - 1202
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1191 KB) | HTML iconHTML

    Commonly used in software design, assertions are statements placed into a design to ensure that its behavior matches that expected by a designer. Although assertions apply equally to hardware design, they are typically supported only for logic simulation, and discarded prior to physical implementation. We propose a new hardware design language-agnostic language for describing latency-insensitive a... View full abstract»

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  • vFlash: Virtualized Flash for Optimizing the I/O Performance in Mobile Devices

    Publication Year: 2017, Page(s):1203 - 1214
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2125 KB) | HTML iconHTML

    I/O is becoming one of major performance bottlenecks in NAND-flash-based mobile devices. Novel nonvolatile memories (NVMs), such as phase change memory and spin-transfer torque random access memory, can provide fast read/write operations. In this paper, we propose a unified NVM/flash architecture to improve the I/O performance. A transparent scheme, virtualized flash (vFlash), is also proposed to ... View full abstract»

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  • Identifying Biases of a Defect Diagnosis Procedure

    Publication Year: 2017, Page(s):1215 - 1225
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1230 KB) | HTML iconHTML

    A defect diagnosis procedure is an important part of the yield improvement process. As defects become more complex, the output responses they produce differ to larger extents from the output responses of modeled faults, and they become more difficult to diagnose. Biases in the defect diagnosis procedure can also cause defects to be more difficult to diagnose. It is important to study and remove su... View full abstract»

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  • Efficient Memristor Model Implementation for Simulation and Application

    Publication Year: 2017, Page(s):1226 - 1230
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (919 KB) | HTML iconHTML

    In this paper, we propose a novel Verilog-A based memristor model for effective simulation and application. Our proposed model captures desired nonlinear characteristics using voltage-based state control. This model is flexible and accurate, it can exhibit all the behaviors of HP memristive device and a general class memristive device resistive random access memory which is important in logic and ... View full abstract»

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  • Clock Sequences for Increasing the Fault Coverage of Functional Test Sequences

    Publication Year: 2017, Page(s):1231 - 1235
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB) | HTML iconHTML

    A functional test sequence for a design may not be effective as a manufacturing test for a logic block in the design because it achieves a low gate-level fault coverage. This paper describes a procedure for selecting a clock sequence that increases the gate-level fault coverage of a functional test sequence when it is used for testing a subset of logic blocks. The procedure deactivates the clocks ... View full abstract»

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  • Introducing IEEE Collabratec

    Publication Year: 2017, Page(s): 1236
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2017, Page(s): C3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors

    Publication Year: 2017, Page(s): C4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu