IEEE Micro

Issue 3 • 2017

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Displaying Results 1 - 25 of 31
  • Front Cover 
  • Front Cover

    Publication Year: 2017, Page(s): c1
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  • New Membership Options for a Better Fit [Advertisement]

    Publication Year: 2017, Page(s): c2
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  • Achieve your career goals with the fit that's right for you [Advertisement]

    Publication Year: 2017, Page(s): 1
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  • Table of Contents 
  • Table of Contents

    Publication Year: 2017, Page(s): 2
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  • Masthead 
  • Masthead

    Publication Year: 2017, Page(s): 3
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  • From the Editor in Chief 
  • Thoughts on the Top Picks Selections

    Publication Year: 2017, Page(s):4 - 5
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  • Guest Editors' Introduction 
  • Top Picks from the 2016 Computer Architecture Conferences

    Publication Year: 2017, Page(s):6 - 11
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  • Top Picks 
  • Using Dataflow to Optimize Energy Efficiency of Deep Neural Network Accelerators

    Publication Year: 2017, Page(s):12 - 21
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (802 KB) | HTML iconHTML

    The authors demonstrate the key role dataflows play in the optimization of energy efficiency for deep neural network (DNN) accelerators. By introducing a systematic approach to analyze the problem and a new dataflow, called Row-Stationary, which is up to 2.5 times more energy efficient than existing dataflows in processing a state-of-the-art DNN, this work provides guidelines for future DNN accele... View full abstract»

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  • The Memristive Boltzmann Machines

    Publication Year: 2017, Page(s):22 - 29
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (718 KB) | HTML iconHTML

    The Boltzmann machine is a massively parallel computational model capable of solving a broad class of combinatorial optimization problems. In recent years, it has successfully been applied to training deep machine learning models on massive datasets. High-performance implementations of the Boltzmann machine using GPUs, MPI-based high-performance computing clusters, and field-programmable gate arra... View full abstract»

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  • Analog Computing in a Modern Context: A Linear Algebra Accelerator Case Study

    Publication Year: 2017, Page(s):30 - 38
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (722 KB) | HTML iconHTML

    Approaching the post-Moore's law era, researchers are looking for scalable ways to get useful computation from existing silicon technology. This article presents a programmable analog accelerator for solving systems of linear equations. The authors compensate for commonly perceived downsides of analog computing, such as low precision and accuracy, limited problem sizes, and difficulty applying it ... View full abstract»

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    Publication Year: 2017, Page(s): 39
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  • Top Picks 
  • Domain Specialization Is Generally Unnecessary for Accelerators

    Publication Year: 2017, Page(s):40 - 50
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (649 KB) | HTML iconHTML

    Domain-specific accelerators (DSAs), which sacrifice programmability for efficiency, are a reaction to the waning benefits of device scaling. This article demonstrates that there are commonalities between DSAs that can be exploited with programmable mechanisms. The goals are to create a programmable architecture that can match the benefits of a DSA and to create a platform for future accelerator i... View full abstract»

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    Publication Year: 2017, Page(s): 51
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  • Top Picks 
  • Configurable Clouds

    Publication Year: 2017, Page(s):52 - 61
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (573 KB) | HTML iconHTML

    Hyperscale datacenter providers have struggled to balance the growing need for specialized hardware with the economic benefits of homogeneity. The Configurable Cloud datacenter architecture introduces a layer of reconfigurable logic (FPGAs) between the network switches and servers. This enables line-rate transformation of network packets, acceleration of local applications running on the server, a... View full abstract»

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  • Specializing a Planet's Computation: ASIC Clouds

    Publication Year: 2017, Page(s):62 - 69
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (613 KB) | HTML iconHTML

    GPU- and FPGA-based clouds have been deployed to accelerate computationally intensive workloads. ASIC-based clouds are a natural evolution as cloud services expand across the planet. ASIC Clouds are purpose-built datacenters comprising large arrays of ASIC accelerators that optimize the total cost of ownership (TCO) of large, high-volume scale-out computations. On the surface, ASIC Clouds may seem... View full abstract»

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  • DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric

    Publication Year: 2017, Page(s):70 - 78
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (418 KB) | HTML iconHTML

    The DRAM-Based Reconfigurable Acceleration Fabric (DRAF) uses commodity DRAM technology to implement a bit-level, reconfigurable fabric that improves area density by 10 times and power consumption by more than 3 times over conventional field-programmable gate arrays. Latency overlapping and multicontext support allow DRAF to meet the performance and density requirements of demanding applications i... View full abstract»

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    Publication Year: 2017, Page(s): 79
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  • Top Picks 
  • Agile Paging for Efficient Memory Virtualization

    Publication Year: 2017, Page(s):80 - 86
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (558 KB) | HTML iconHTML

    Virtualization provides benefits for many workloads, but the overheads of virtualizing memory are still high. The cost comes from managing two levels of address translation--one in the guest virtual machine (VM) and the other in the host virtual machine monitor (VMM)--with either nested or shadow paging. This article introduces agile paging, which combines the best of both nested and shadow paging... View full abstract»

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  • IEEE Computer Society Harlan D. Mills Award

    Publication Year: 2017, Page(s): 87
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  • Top Picks 
  • Transistency Models: Memory Ordering at the Hardware-OS Interface

    Publication Year: 2017, Page(s):88 - 97
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (725 KB) | HTML iconHTML

    This article introduces the transistency model, a set of memory ordering rules at the intersection of virtual-to-physical address translation and memory consistency models. Using their COATCheck tool, the authors show how to rigorously model, analyze, and verify the correctness of a given system's microarchitecture and software stack with respect to its transistency model specification. View full abstract»

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  • Toward a DNA-Based Archival Storage System

    Publication Year: 2017, Page(s):98 - 104
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (669 KB) | HTML iconHTML

    Storing data in DNA molecules offers extreme density and durability advantages that can mitigate exponential growth in data storage needs. This article presents a DNA-based archival storage system, performs wet lab experiments to show its feasibility, and identifies technology trends that point to increasing practicality. View full abstract»

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  • IEEE Cloud Computing Call for Papers

    Publication Year: 2017, Page(s): 105
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  • Top Picks 
  • Ti-States: Power Management in Active Timing Margin Processors

    Publication Year: 2017, Page(s):106 - 114
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (838 KB) | HTML iconHTML

    Temperature inversion is a transistor-level effect that improves performance when temperature increases. This article presents a comprehensive measurement-based analysis on temperature inversion's implications on architecture design and power management using the AMD A10-8700P processor. The authors propose temperature-inversion states (Ti-states) to harness the opportunities promised by temperatu... View full abstract»

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    Publication Year: 2017, Page(s): 115
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  • Top Picks 
  • An Energy-Aware Debugger for Intermittently Powered Systems

    Publication Year: 2017, Page(s):116 - 125
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (651 KB) | HTML iconHTML

    Energy-harvesting technology has the potential to free computing devices from the constraints of wires and batteries. However, writing software for energy-harvesting computers is uniquely challenging. Programs on energy-harvesting devices execute intermittently due to frequent power failures. Intermittent execution can create errors that are not possible in continuously powered systems and that ar... View full abstract»

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Aims & Scope

IEEE Micro addresses users and designers of microprocessors and microprocessor systems, including managers, engineers, consultants, educators, and students involved with computers and peripherals, components and subassemblies, communications, instrumentation and control equipment, and guidance systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Erik R. Altman
School of Electrical and Computer Engineering
IBM T.J. Watson Research Center