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Electron Device Letters, IEEE

Issue 12 • Date Dec. 1994

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Displaying Results 1 - 10 of 10
  • Transistor performance and electron transport properties of high performance InAs quantum-well FET's

    Page(s): 489 - 492
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (379 KB)  

    A novel field-effect transistor based on a pseudomorphic InAs quantum well in a doped InGaAs/InAlAs double heterostructure is reported. Low-field mobility, electron peak velocity, and transistor performance are studied as functions of InAs quantum well thickness, where the InAs layer is in the center of a 300-/spl Aring/ uniformly doped InGaAs/InAlAs quantum well lattice matched to InP. Electron transport-both at low and high fields-along with transistor transconductance are optimal for structures with a 30-/spl Aring/ InAs quantum well. Transistors based on the InAs quantum well structures with 0.5-μm gate lengths yielded room temperature extrinsic transconductances of 708 mS/mm, more than a 100% increase over those with no InAs. View full abstract»

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  • Enhanced high-frequency performance in a GaAs, self-aligned, n-JFET using a carbon buried p-implant

    Page(s): 493 - 495
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    C ion implantation has been employed, for the first time, to form the buried p-layer in GaAs, self-aligned, ion implanted JFETs. Comparable DC performance was seen for JFETs with C or Mg implants; however, C-backside JFETs showed superior high-frequency performance. High dose C-backside devices had a fT of 28.3 GHz and a fmax of 43.2 GHz for a 0.5 μm gate length that were 28% and 46% higher, respectively, than comparable Mg-implanted JFETs. This enhancement is a result of the lower C/sub gs/ in the C-backside device resulting from he inherently low activation of the implanted C below the channel while the C still effectively compensated the tail of the Si-channel implant. This approach relaxes the trade-off between optimizing the DC and the AC performance for the buried p-implant in GaAs JFETs and MESFET's. View full abstract»

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  • Anomalous narrow channel effect in trench-isolated buried-channel p-MOSFET's

    Page(s): 496 - 498
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    An anomalous threshold voltage dependence on channel width measured on 0.25 μm groundrule trench-isolated buried-channel p-MOSFET's is reported here. As the channel width is reduced, the magnitude of the threshold voltage first decreases before the onset of the expected sharp rise in Vt for widths narrower than 0.4 μm. Modeling shows that a "boron puddle" is created near the trench bounded edge as a result of transient enhanced diffusion (TED) during the gate oxidation step. TED is governed by interstitials produced by a deep phosphorus implant, used for latchup suppression, diffusing towards the trench sidewall and top surface of the device. The presence of the "boron puddle" imposes a penalty on the off-current of narrow devices. A solution for minimizing the "boron puddle" is demonstrated with simulations, confirmed by measurements. View full abstract»

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  • Hot-carrier induced electron mobility and series resistance degradation in LDD NMOSFET's

    Page(s): 499 - 501
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    The mobility and the series resistant degradation of LDD NMOSFET's were determined independently for the first time. Three device structures with different styles of drain engineering: 1) modestly doped LDD; 2) large-angle-tilt implanted drain, and 3) buried LDD were studied. We observed clearly that the series resistant drift dominates the initial device degradation and the relative importance of the mobility degradation increases as the stress time proceeds. Our work provides a useful guideline for device reliability optimization and for the development of the device degradation model for the circuit reliability simulation.<> View full abstract»

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  • High-performance p-channel poly-Si TFT's using electron cyclotron resonance hydrogen plasma passivation

    Page(s): 502 - 503
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    This letter presents a summary of the first detailed investigation of electron cyclotron resonance (ECR) hydrogen plasma exposure treatments of p-channel poly-Si thin film transistors (TFT's). It is shown that ECR hydrogenation can be much more efficient than RF hydrogenation. Poly-Si p-channel TFT's fabricated at low temperatures (/spl les/625/spl deg/C) and passivated with the ECR hydrogenation treatment are shown to exhibit ON/OFF current ratios of 7.6/spl times/10/sup 7/, subthreshold swings of 0.62 V/decade, threshold voltages of -4.6 V, and hole mobilities over 18 cm/sup 2//V.s.<> View full abstract»

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  • Channel length dependence of random telegraph signal in sub-micron MOSFET's

    Page(s): 504 - 506
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (254 KB)  

    The channel length dependence of the random telegraph signal (RTS) in a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has been investigated both theoretically and experimentally. The key result is that, for a given surface potential, the RTS amplitude is proportional to 1/L/sup 2/, where L is the channel length, provided the contribution of the mobility fluctuation is much smaller than that of the carrier number fluctuation. A special test structure, consisting of a series combination of MOSFET's, is used to experimentally determine this channel length dependence, and good agreement with our simple theory is obtained.<> View full abstract»

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  • Visible electroluminescence from stain-etched porous Si diodes

    Page(s): 507 - 509
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    Visible electroluminescence (EL) from stain-etched porous silicon (PoSi) films is presented. The PoSi thin layers (/spl sim/200 nm) were obtained by stain-etching of B-doped 6-16 /spl Omega/-cm [100] crystalline Si in a HF:HNO/sub 3/:H/sub 2/O (1:3:5) solution. Indium tin oxide (ITO) films of /spl sim/2500 /spl Aring/ were used to form a Schottky contact. Visible EL was observed at room temperature from the diode under forward bias. EL onset bias as low as 3 mA/cm/sup 2/ was measured. The EL, with an emission peak at /spl sim/640 nm, is similar to the photoluminescence under UV excitation, indicating the same luminescent centers. This result demonstrates a promising and simple technique for the fabrication of PoSi-based light emitting diodes and flat panel display devices.<> View full abstract»

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  • A dynamic threshold voltage MOSFET (DTMOS) for very low voltage operation

    Page(s): 510 - 512
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    A new mode of operation for Silicon-On-Insulator (SOI) MOSFET is experimentally investigated. This mode gives rise to a Dynamic Threshold voltage MOSFET (DTMOS). DTMOS threshold voltage drops as gate voltage is raised, resulting in a much higher current drive than regular MOSFET at low V/sub dd/. On the other hand, V/sub t/ is high at V/sub gs/=0, thus the leakage current is low. Suitability of this device for ultra low voltage operation is demonstrated by ring oscillator performance down to V/sub dd/=0.5 V.<> View full abstract»

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  • Effects of controlled texturization of the crystalline Si surface on the SiO/sub 2//Si effective barrier height

    Page(s): 513 - 515
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    A two-stage plasma etch texturination process to control the level of crystalline silicon surface roughness has been investigated. Initially, a Cl/sub 2/ plasma etch is used to produce a very rough Si surface. This is followed by an isotropic SF/sub 6/ plasma etch, whose etch time is used to reduce and control the level of surface roughness created by the previous step. Oxides grown on texturized Si surfaces with short SF/sub 6/ etch times exhibit lower effective SiO/sub 2//Si barrier height and greater electron injection enhancement than those with longer SF/sub 6/ etch times.<> View full abstract»

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  • The electrical properties of sub-5-nm oxynitride dielectrics prepared in a nitric oxide ambient using rapid thermal processing

    Page(s): 516 - 518
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    Ultrathin (<5 nm) dielectric films have been grown on <100> silicon using rapid thermal processing (RTP) in a nitric oxide (NO) ambient. Interface state density, charge trapping properties, and interface state generation during Fowler-Nordheim electron injection have been investigated. The films grown in NO have excellent electrical properties. These properties are explained in terms of a much stronger and large number of Si-N bonds in both the bulk of the dielectric films and at the Si-SiO/sub 2/ interface region. The leakage currents are at least three orders of magnitude lower than other reported results for similar thicknesses. The dielectric films grown in NO ambient are viewed as promising technology for ultrathin dielectrics.<> View full abstract»

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