IEEE Embedded Systems Letters

Issue 2 • June 2017

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Displaying Results 1 - 11 of 11
  • Table of contents

    Publication Year: 2017, Page(s): C1
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  • IEEE Embedded Systems Letters publication information

    Publication Year: 2017, Page(s): C2
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  • HybridVerifier: A Cross-Platform Verification Framework for Instruction Set Simulators

    Publication Year: 2017, Page(s):25 - 28
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (676 KB) | HTML iconHTML

    Instruction set simulators (ISSs) play a critical role in the design cycle of embedded systems. However, as ISSs evolve and increase in complexity, not only new bugs might be introduced but also old latent bugs might be revealed. Finding these bugs based on the simulator output might be a challenging task. This letter presents HybridVerifier, a novel and retargetable framework for ISS verification... View full abstract»

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  • LH-CAM: Logic-Based Higher Performance Binary CAM Architecture on FPGA

    Publication Year: 2017, Page(s):29 - 32
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (353 KB) | HTML iconHTML

    Binary content-addressable memory (BiCAM) is a popular high speed search engine in hardware, which provides output typically in one clock cycle. But speed of CAM comes at the cost of various disadvantages, such as high latency, low storage density, and low architectural scalability. In addition, field-programmable gate arrays (FPGAs), which are used in many applications because of its advantages, ... View full abstract»

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  • Subleq $_circleddash$ : An Area-Efficient Two-Instruction-Set Computer

    Publication Year: 2017, Page(s):33 - 36
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1215 KB) | HTML iconHTML

    Applications with strict resource/power constraints demand the research and development of area-efficient processor designs that deliver reasonably good performance with small circuit area. While the ARM and RISC-V instruction set architecture (ISAs) are lightweight alternatives to ×86, they nevertheless consume considerable circuit area and power. In this letter, we return to a fundamental... View full abstract»

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  • Implicit Programming: A Fast Programming Strategy for nand Flash Memory Storage Systems Adopting Redundancy Methods

    Publication Year: 2017, Page(s):37 - 40
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (597 KB) | HTML iconHTML

    The aggressive shrinking of process geometry and an increase in the number of bits stored in each memory cell of NAND flash memory inevitably degrade the reliability of NAND flash. Redundancy methods have been widely adopted to enhance the reliability of the system data in NAND flash memory. However, the redundancy process will induce extra program operations which will sharply degrade the I/O per... View full abstract»

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  • A Novel Micro-Architecture Using a Simplified Logistic Map for Embedded Security

    Publication Year: 2017, Page(s):41 - 44
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (317 KB) | HTML iconHTML

    A novel scheme for the introduction of chaos-based security into embedded systems at an architectural (hardware) level is presented in this letter. The logistic map is simplified for use in resource-constrained microcontrollers in the encryption of digital data through interface protocols like SPI etc. This letter, as an example, presents an outline of the registers and their associated logic for ... View full abstract»

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  • Lightweight Prediction-Based Tests for On-Line Min-Entropy Estimation

    Publication Year: 2017, Page(s):45 - 48
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (843 KB) | HTML iconHTML

    Health tests (on-the-fly tests) play an important role in true random number generators because they are used to assess the quality of the bits produced by entropy source and to raise an alert when failures or attacks are detected. Most of classical tests are implemented as statistical tests. A set of new health tests based on predictors was presented by National Institute of Standards and Technol... View full abstract»

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  • Performance Evaluation of Network-on-Chip-Based H.264 Video Decoders via Full System Simulation

    Publication Year: 2017, Page(s):49 - 52
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (629 KB) | HTML iconHTML

    We present a full system simulation framework for a network-on-chip (NoC)-based H.264 video decoder. By combining both the communication, i.e., the NoC and the processing, i.e., H.264 modules, components into the same simulation framework, we present for the first time the capability of simulating NoCs exercised with truly real traffic. Such a simulator can be utilized to evaluate performance metr... View full abstract»

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  • IEEE Embedded Systems Letters information for authors

    Publication Year: 2017, Page(s): C3
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  • Blank page

    Publication Year: 2017, Page(s): C4
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Aims & Scope

The IEEE Embedded Systems Letters (ESL), provides a forum for rapid dissemination of latest technical advances in embedded systems and related areas in embedded software.

Full Aims & Scope

Meet Our Editors

EDITOR-IN-CHIEF
Sri Parameswaran
School of Computer Science and Engineering
University of New South Wales

DEPUTY EDITOR-IN-CHIEF
Tulika Mitra
School of Computing
National University of Singapore