IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 6 • June 2017

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  • Table of contents

    Publication Year: 2017, Page(s): C1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2017, Page(s): C2
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  • Experience of Data Analytics in EDA and Test—Principles, Promises, and Challenges

    Publication Year: 2017, Page(s):885 - 898
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1542 KB) | HTML iconHTML

    Applying modern data mining in electronic design automation and test has become an area of growing interest in recent years. This paper reviews some of the recent developments in the area. It begins by introducing several key concepts in machine learning and data mining, followed by a review of different learning approaches. Then, the experience of developing a practical data mining application is... View full abstract»

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  • C-YES: An Efficient Parametric Yield Estimation Approach for Analog and Mixed-Signal Circuits Based on Multicorner-Multiperformance Correlations

    Publication Year: 2017, Page(s):899 - 912
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2018 KB) | HTML iconHTML

    Parametric yield estimation is a critical task for design and validation of analog and mixed-signal (AMS) circuits. However, the computational cost for yield estimation based on Monte Carlo (MC) analysis is often prohibitively high, especially when multiple circuit performances and/or environmental corners (e.g., voltage and temperature corners) are considered. In this paper, a novel statistical m... View full abstract»

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  • Mask Assignment and DSA Grouping for DSA-MP Hybrid Lithography for Sub-7 nm Contact/Via Holes

    Publication Year: 2017, Page(s):913 - 926
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1953 KB) | HTML iconHTML

    Directed self assembly (DSA) is a very promising candidate for the sub-7 nm technology nodes. To print such small dimensions, multiple patterning (MP) is likely to be used to print the guiding templates for DSA. Therefore, algorithms are required to perform the DSA grouping at the same time as the mask assignment. In this paper, we present an optimal integer linear program (ILP) to solve this prob... View full abstract»

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  • Reconfigurable Constant Multiplication for FPGAs

    Publication Year: 2017, Page(s):927 - 937
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1365 KB) | HTML iconHTML

    This paper introduces a new heuristic to generate pipelined run-time reconfigurable constant multipliers for field-programmable gate arrays (FPGAs). It produces results close to the optimum. It is based on an optimal algorithm which fuses already optimized pipelined constant multipliers generated by an existing heuristic called reduced pipelined adder graph (RPAG). Switching between different sing... View full abstract»

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  • A Structured Visual Approach to GALS Modeling and Verification of Communication Circuits

    Publication Year: 2017, Page(s):938 - 951
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1709 KB) | HTML iconHTML

    In this paper, a novel globally asynchronous locally synchronous (GALS) modeling and verification tool is introduced for xMAS circuits. The tool provides a structured environment for GALS in which organization of the modeling and verification enables it to handle a variety of implementation tasks facilitating a process which would otherwise be difficult for the end user. The tool provides verifica... View full abstract»

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  • One-Sided Net Untangling With Internal Detours for Bus Routing

    Publication Year: 2017, Page(s):952 - 963
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1243 KB) | HTML iconHTML

    It is known that it is necessary for single-layer bus routing to untangle all the twisted nets inside a single bus. In this paper, the concept of using internal detours on untangled nets can be introduced to solve the unroutable conditions in one-sided single-detour untangling. Based on the optimality-oriented swap passes in Yan's hierarchical bubble sorting, given a set of two-pin nets inside a s... View full abstract»

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  • Nanowire-Aware Routing Considering High Cut Mask Complexity

    Publication Year: 2017, Page(s):964 - 977
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3094 KB) | HTML iconHTML

    1-D nanowires are one of the most promising next-generation lithography technologies for 7 nm process node and beyond. The 1-D nanowire process first constructs a 1-D nanoarray through template synthesis followed by line-end cutting with additional cut masks. To achieve better yield and manufacturability, the cut patterns shall satisfy specified restricted design rules, and thus it is desirable to... View full abstract»

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  • Silica-Embedded Silicon Nanophotonic On-Chip Networks

    Publication Year: 2017, Page(s):978 - 991
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (11538 KB) | HTML iconHTML

    On-chip nanophotonics offer high throughput, yet energy-efficient communication, traits that can prove critical to the continuance of multicore chip scalability. In this paper, we investigate and propose silicon nanophotonic components that are embedded entirely in the silica (SiO2) substrate, i.e., reside subsurface, as opposed to die on-surface silicon nanophotonics of prior-art. Amon... View full abstract»

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  • Full Chip Impact Study of Power Delivery Network Designs in Gate-Level Monolithic 3-D ICs

    Publication Year: 2017, Page(s):992 - 1003
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3154 KB) | HTML iconHTML

    In this paper, we present a comprehensive study on the impact of power delivery network (PDN) on full-chip wirelength, routability, power, and thermal effects in gate-level monolithic 3-D (M3-D) ICs across different technology nodes. Our studies show that PDN worsens routing congestion more severely in M3-D ICs than in 2-D designs due to the significant reduction in resources for 3-D connections. ... View full abstract»

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  • Built-In Test and Diagnosis for TSVs With Different Placement Topologies and Crosstalk Impact Ranges

    Publication Year: 2017, Page(s):1004 - 1017
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2869 KB) | HTML iconHTML

    Through silicon vias (TSVs) play an important role in 3-D chip integration. Effective and efficient testing for correct operation of TSVs is essential for 3-D integrated circuit design. This paper addresses the post-bond test and diagnosis of crosstalk faults among TSVs considering different impact ranges, and proposes a TSV grouping method for rectangular and hexagonal TSV placements such that as... View full abstract»

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  • More Efficient Testing of Metal-Oxide Memristor–Based Memory

    Publication Year: 2017, Page(s):1018 - 1029
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1766 KB) | HTML iconHTML

    Resistive memory is a promising emerging technology but is prone to defects due to uncertainties in nanoscale fabrication. The test time of existing techniques for bipolar metal-oxide memristors is dominated by slow writes. Fast March tests are proposed that benefit from fast write operations. The test application time is reduced significantly while simultaneously reducing the average test energy ... View full abstract»

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  • ExTest Scheduling and Optimization for 2.5-D SoCs With Wrapped Tiles

    Publication Year: 2017, Page(s):1030 - 1042
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2346 KB) | HTML iconHTML

    Interposer-based 2.5-D integrated circuits (ICs) enable high-density interconnects, but introduce new challenges for the testing of a system-on-chip (SoC) die on an interposer. This paper presents two efficient ExTest scheduling strategies that implements interconnect testing between tiles inside an SoC die while satisfying the practical constraint that the number of required test pins cannot exce... View full abstract»

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  • Adaptive Reduction of the Frequency Search Space for Multi- $V_{\mathrm{ dd}}$ Digital Circuits Using Variation Sensitive Ring Oscillators

    Publication Year: 2017, Page(s):1043 - 1053
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1238 KB) | HTML iconHTML

    Increasing process variations, coupled with the need for highly adaptable circuits, bring about tough new challenges regarding circuit testing. Circuit adaptation for process and workload variability require costly characterization/test cycles for each chip, to extract particular Vdd/fmax behavior of the device under test (DUT). Consequently, the test cost associated with fre... View full abstract»

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  • Optimal Greedy Algorithm for Many-Core Scheduling

    Publication Year: 2017, Page(s):1054 - 1058
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB) | HTML iconHTML

    In this paper, we propose an optimal greedy algorithm for the problem of run-time many-core scheduling. The previously best known centralized optimal algorithm proposed for the problem is based on dynamic programming. A dynamic programming-based scheduler has high overheads which grow fast with increase in both the number of cores in the many-cores as well as number of tasks independently executin... View full abstract»

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  • Introducing IEEE Collabratec

    Publication Year: 2017, Page(s): 1059
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  • Together, we are advancing technology

    Publication Year: 2017, Page(s): 1060
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2017, Page(s): C3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors

    Publication Year: 2017, Page(s): C4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu