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IEEE Design & Test

Issue 3 • June 2017

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Displaying Results 1 - 22 of 22
  • Front Cover

    Publication Year: 2017, Page(s): C1
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  • Cover 2

    Publication Year: 2017, Page(s): C2
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  • IEEE Design&Test publication information

    Publication Year: 2017, Page(s): 1
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  • Table of Contents

    Publication Year: 2017, Page(s):2 - 3
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  • Emerging Memory Technologies

    Publication Year: 2017, Page(s):4 - 5
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  • Guest Editors’ Introduction: Critical and Enabling Techniques for Emerging Memories

    Publication Year: 2017, Page(s):6 - 7
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  • Recent Technology Advances of Emerging Memories

    Publication Year: 2017, Page(s):8 - 22
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2253 KB) | HTML iconHTML

    Phase change memory, spin-transfer torque random access memory, and resistive random access memory are three major emerging memory technologies that receive tremendous attentions from both academia and industry. In this survey article, the authors summarize the latest research progress of these technologies in device engineering, circuit design, computer architecture, and application. View full abstract»

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  • Correlated Effects on Forming and Retention of Al Doping in HfO2-Based RRAM

    Publication Year: 2017, Page(s):23 - 30
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1811 KB) | HTML iconHTML

    Retention time is one of the key parameters of emerging memories, which define the time duration the data can be retained when the power supply is removed. In this work, the authors investigate the forming voltage and the data retention of aluminum (Al)-doped HfO2-based RRAM devices and suggest a way to improve the device's data retention time. View full abstract»

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  • Reliable Nonvolatile Memories: Techniques and Measures

    Publication Year: 2017, Page(s):31 - 41
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (113 KB) | HTML iconHTML

    Reliability continues to be a severe challenge in the development of emerging memories. In this article, the authors offer a comprehensive survey of reliability enhancement techniques for three mainstream emerging memories and a summary of the possible future research directions in this area. View full abstract»

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  • Multisource Indoor Energy Harvesting for Nonvolatile Processors

    Publication Year: 2017, Page(s):42 - 49
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (690 KB) | HTML iconHTML

    One promising application of emerging memories is to implement a nonvolatile memory hierarchy that can retain the data when power is removed. In this work, the authors present some design techniques of nonvolatile processors with a multisource energy-harvesting system that combines thermal, kinetic, and indoor photovoltaic sources to provide a stable power supply. View full abstract»

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  • Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package

    Publication Year: 2017, Page(s):50 - 58
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1382 KB) | HTML iconHTML

    Editor's note: To reduce the manufacturing cost of heterogeneous 3-D integration, the Integrated Fan-Out Wafer-Level Chip-Scale Packaging (InFO WLCSP) is one of the emerging packaging technologies. In this article, the authors propose a cost model for InFO WLCSP, which can be used for analyzing the total test cost with respect to the test configuration and for optimizing the test configuration and... View full abstract»

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  • Interdependencies of Degradation Effects and Their Impact on Computing

    Publication Year: 2017, Page(s):59 - 67
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1306 KB) | HTML iconHTML

    Editor's note: Process variations, aging and wearout, are nonidealities that lead to suboptimal system performance and increased power. In order to understand the effects of these degradation effects, until now, researchers have investigated them thoroughly, but separately from each other. What this article shows is that process variations and wearout are not independent from each other and they n... View full abstract»

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  • Post-Silicon Validation in the SoC Era: A Tutorial Introduction

    Publication Year: 2017, Page(s):68 - 92
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2145 KB) | HTML iconHTML

    Editor's note: Post-silicon validation is a complex and critical component of a modern system-on-chip (SoC) design verification. It includes a large number of inter-related activities each with its own nuance and subtleties, requires extensive planning, and spans the entire system design lifecycle. This article provides a comprehensive high-level overview of the various facets of post-silicon vali... View full abstract»

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  • Quo Vadis Test? The Past, the Present, and the Future: No Longer a Necessary Evil

    Publication Year: 2017, Page(s):93 - 95
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (195 KB) | HTML iconHTML

    For a long time, test was considered to be an afterthought in the design and manufacturing of integrated circuits. Designers were the heroes of the industry and the foundry was the magical (and mysterious) place where wafers were produced and revenue generated. The test engineers worked in the background-quietly and without much fuss-and they were there just to catch the chips that were tossed to ... View full abstract»

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  • Designing Secure Electronics: Challenges From a Hardware Perspective

    Publication Year: 2017, Page(s):96 - 102
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  • Recap of the 22nd Asia and South- Pacific Design Automation Conference

    Publication Year: 2017, Page(s):103 - 104
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  • Cyber-Physical System Design With Sensor Networking Technologies

    Publication Year: 2017, Page(s):105 - 107
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  • Code Ocean Is Live: Upload Your Algorithms

    Publication Year: 2017, Page(s):108 - 109
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  • Test Technology TC Newsletter

    Publication Year: 2017, Page(s):110 - 111
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  • Being Connected

    Publication Year: 2017, Page(s): 112
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  • Cover 3

    Publication Year: 2017, Page(s): C3
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  • Cover 4

    Publication Year: 2017, Page(s): C4
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Aims & Scope

IEEE Design & Test offers original works describing the models, methods and tools used to design and test microelectronic systems from devices and circuits to complete systems-on-chip and embedded software. The magazine focuses on current and near-future practice, and includes tutorials, how-to articles, and real-world case studies. The magazine seeks to bring to its readers not only important technology advances but also technology leaders, their perspectives through its columns, interviews and roundtable discussions. Topics include semiconductor IC design, semiconductor intellectual property blocks, design, verification and test technology, design for manufacturing and yield, embedded software and systems, low-power and energy efficient design, electronic design automation tools, practical technology, and standards.  

It was published as IEEE Design & Test of Computers between 1984 and 2012.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Joerg Henkel
Chair for Embedded Systems (CES)
Karlsruhe Institute of Technology (KIT)