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# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

## Filter Results

Displaying Results 1 - 24 of 24

Publication Year: 2017, Page(s):C1 - C4
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Publication Year: 2017, Page(s): C2
| PDF (78 KB)
• ### Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology

Publication Year: 2017, Page(s):1593 - 1600
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In this paper, a novel radiation-hardened-by-design (RHBD) 12T memory cell is proposed to tolerate single node upset and multiple-node upset based on upset physical mechanism behind soft errors together with reasonable layout-topology. The verification results obtained confirm that the proposed 12T cell can provide a good radiation robustness. Compared with 13T cell, the increased area, power, rea... View full abstract»

• ### An Enhancement of Crosstalk Avoidance Code Based on Fibonacci Numeral System for Through Silicon Vias

Publication Year: 2017, Page(s):1601 - 1610
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Through silicon vias (TSVs) play an important role as the vertical electrical connections in 3-D stacked integrated circuits. However, the closely clustered TSVs suffer from the crosstalk noise between the neighboring TSVs, and result in the extra delay and the deterioration of signal integrity. For a 3 × 3 TSV array, the severity of crosstalk noise in the center victim TSV is classified in... View full abstract»

• ### A Multilayer Approach to Designing Energy-Efficient and Reliable ReRAM Cross-Point Array System

Publication Year: 2017, Page(s):1611 - 1621
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In this paper, we study the 1-selector1-resistor (1S1R) cross-point resistive random access memory (ReRAM) array because of its high density, fast access time, and ultralow stand-by power. Specifically, we focus on an access scheme where a data line is parallelly accessed from multiple subarrays with multibits accessed per subarray. A direct implementation of such a scheme has high energy efficien... View full abstract»

• ### A Fast and Reliable Cross-Point Three-State/Cell ReRAM

Publication Year: 2017, Page(s):1622 - 1631
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We present a fast and reliable fully integrated cross-point three-state cell resistive random access memory. We accomplish swift back-and-forth hopping among the three resistance states by current-limiting set and in situ bit line regulating reset writing. The self-stuffing word line driver alleviates resistance variations in medium and low resistance states by 2.3 times and 3 times, respectively.... View full abstract»

• ### Digit-Level Serial-In Parallel-Out Multiplier Using Redundant Representation for a Class of Finite Fields

Publication Year: 2017, Page(s):1632 - 1643
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Two digit-level finite field multipliers in F2m using redundant representation are presented. Embedding F2m in cyclotomic field F2(n) causes a certain amount of redundancy and consequently performing field multiplication using redundant representation would require more hardware resources. Based on a specific feature of redundant re... View full abstract»

• ### Time-Encoded Values for Highly Efficient Stochastic Circuits

Publication Year: 2017, Page(s):1644 - 1657
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Stochastic computing (SC) is a promising technique for applications that require low area overhead and fault tolerance, but can tolerate relatively high latency. In the SC paradigm, logical computation is performed on randomized bit streams. In prior work, streams were generated with linear feedback shift registers; these contributed heavily to the hardware cost and consumed a significant amount o... View full abstract»

• ### A General Digit-Serial Architecture for Montgomery Modular Multiplication

Publication Year: 2017, Page(s):1658 - 1668
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The Montgomery algorithm is a fast modular multiplication method frequently used in cryptographic applications. This paper investigates the digit-serial implementations of the Montgomery algorithm for large integers. A detailed analysis is given and a tight upper bound is presented for the intermediate results obtained during the digit-serial computation. Based on this analysis, an efficient digit... View full abstract»

• ### Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond

Publication Year: 2017, Page(s):1669 - 1680
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In an increasing interconnect resistance era and aggressive metal pitch scaling, the elevating RC delay could significantly shadow the improvements from advanced device architectures and become a severe design issue. This paper will holistically analyze the interplay between transistors and interconnect delay and the variability induced by back-end-ofline (BEOL) process for the 5-nm node. A global... View full abstract»

• ### Error-Resilient Integrated Clock Gate for Clock-Tree Power Optimization on a Wide Voltage IOT Processor

Publication Year: 2017, Page(s):1681 - 1693
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Energy-efficiency optimization occupies an important position in the Internet of Things application. The error-resilience technique has begun to emerge and brought the performance and energy benefits as a new vision for alternative computing, because it eliminates the overconstrained margin in current processor design flow and protects the system from process, supply voltage, temperature, and agin... View full abstract»

• ### Design and Applications of Approximate Circuits by Gate-Level Pruning

Publication Year: 2017, Page(s):1694 - 1702
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Energy-efficiency is a critical concern for many systems, ranging from Internet of things objects and mobile devices to high-performance computers. Moreover, after 40 years of prosperity, Moore's law is starting to show its economic and technical limits. Noticing that many circuits are over-engineered and that many applications are error-resilient or require less precision than offered by the exis... View full abstract»

• ### NaPer: A TSV Noise-Aware Placer

Publication Year: 2017, Page(s):1703 - 1713
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Through-silicon-via (TSV)-to-TSV coupling issue can degrade the signal integrity in 3-D integrated circuit designs. This paper develops a 3-D partitioning-based force-directed placer, NaPer, to reduce the total coupling noise between TSVs and alleviate the maximum coupling noise between them. We introduce two denoise forces: TSV decoupling force and TSV density force. The TSV decoupling force is d... View full abstract»

• ### Hardware Architecture Based on Parallel Tiled QRD Algorithm for Future MIMO Systems

Publication Year: 2017, Page(s):1714 - 1724
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QR decomposition (QRD) has been a vital component in the transceiver processor of future multiple-input multiple-output (MIMO) systems, in which antenna configuration will be more and more flexible. Therefore, the QRD hardware architecture in the future MIMO systems should be more flexible to meet various antenna configurations. Unfortunately, the existing QRD hardware architectures mainly focus o... View full abstract»

• ### Design of a CMOS Chlorophyll Concentration Detector Based on Organic Chlorophyll Battery for Measuring Vegetable Chlorophyll Concentration

Publication Year: 2017, Page(s):1725 - 1730
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In this paper, a CMOS chlorophyll concentration detector based on organic chlorophyll battery for measuring vegetable chlorophyll concentration is newly proposed. The organic chlorophyll battery and analog processing circuits are compactly and robustly cooperated. Comparing with previous works, the proposed chlorophyll concentration detector can be possibly easy and low-cost realized by users. All... View full abstract»

• ### An Inductive 2-D Position Detection IC With 99.8% Accuracy for Automotive EMR Gear Control System

Publication Year: 2017, Page(s):1731 - 1741
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In this paper, the analog front end (AFE) for an inductive position sensor in an automotive electromagnetic resonance gear control applications is presented. To improve the position detection accuracy, a coil driver with an automatic two-step impedance calibration is proposed which, despite the load variation, provides the desired driving capability by controlling the main driver size. Also, a tim... View full abstract»

• ### A 6-mW, 70.1-dB SNDR, and 20-MHz BW Continuous-Time Sigma-Delta Modulator Using Low-Noise High-Linearity Feedback DAC

Publication Year: 2017, Page(s):1742 - 1755
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A 4-bit, third-order, continuous-time ΣA modulator is presented for use in wireless communications systems. Based on small-signal noise models, analyses for reducing noise in the feedback digital-to-analog converter (DAC) are presented in detail. This enables easy performance/area optimization for the DAC unit elements and the RC noise filter in the DAC bias circuits. To obtain high lineari... View full abstract»

• ### A 170-dB $\Omega$ CMOS TIA With 52-pA Input-Referred Noise and 1-MHz Bandwidth for Very Low Current Sensing

Publication Year: 2017, Page(s):1756 - 1766
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A fully integrated current sensing interface chip employing a capacitive-feedback transimpedance amplifier (TIA) is presented. A robust dc current removal block is proposed to prevent the dc portion of the input current from saturating the output voltage. This block allows the TIA to operate in the presence of a wide range of input dc currents, and the cancellation loop is designed to enhance its ... View full abstract»

• ### 28-nm Latch-Type Sense Amplifier Modification for Coupling Suppression

Publication Year: 2017, Page(s):1767 - 1773
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With the development of modern semiconductor fabrication technology, the channel length of the CMOS device and the device pitch continually shrink accompanied by more and more severe process variation and signal coupling effect, respectively. In this paper, we explain how the coupling effect interferes with the action of the sense amplifier (SA); then we introduce a coupling suppressed SA. In our ... View full abstract»

• ### Floating Gate Nonvolatile Memory Using Individually Cladded Monodispersed Quantum Dots

Publication Year: 2017, Page(s):1774 - 1781
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This paper presents nonvolatile memory characteristics of a quantum dot gate floating gate nonvolatile memory (QDNVM) that employs SiOx-cladded silicon quantum dots as discrete charge storage nodes of the floating gate. The cladding of Si quantum dots and control of their size are shown to result in a faster access and improved retention time. The floating gate is formed by site-specifi... View full abstract»

• ### Design of Power and Area Efficient Approximate Multipliers

Publication Year: 2017, Page(s):1782 - 1786
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Approximate computing can decrease the design complexity with an increase in performance and power efficiency for error resilient applications. This brief deals with a new design approach for approximation of multipliers. The partial products of the multiplier are altered to introduce varying probability terms. Logic complexity of approximation is varied for the accumulation of altered partial pro... View full abstract»

• ### Two-Extra-Column Trellis Min–Max Decoder Architecture for Nonbinary LDPC Codes

Publication Year: 2017, Page(s):1787 - 1791
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In this brief, a novel two-extra-column trellis min-max algorithm and the decoder architecture based on only the first minimum values are proposed for nonbinary low-density parity-check (NB-LDPC) codes. The algorithm greatly reduces the hardware complexity and improves the latency as well as the throughput of the proposed decoder architecture compared with the previous works. A layered decoder arc... View full abstract»

• ### Corrections to “Crosstalk-Canceling Multimode Interconnect Using Transmitter Encoding”[ Aug 13 1562-1567]

Publication Year: 2017, Page(s): 1792
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The authors of [1] would like to note the following corrections in reference numbering. It is difficult to find correct references in the currently published paper due to the reference discords. View full abstract»

• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Publication Year: 2017, Page(s): C3
| PDF (52 KB)

## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu