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# IEEE Transactions on Circuits and Systems II: Express Briefs

## Filter Results

Displaying Results 1 - 25 of 31

Publication Year: 2017, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—II:Express Briefs publication information

Publication Year: 2017, Page(s): C2
| PDF (64 KB)
• Analog and Mixed Mode Circuits and Systems
• ### Calibration of Time-Interleaved ADCs via Hermitianity-Preserving Taylor Approximations

Publication Year: 2017, Page(s):357 - 361
| | PDF (938 KB)

A new calibration technique for time-interleaved analog-to-digital converters is proposed, based on Hermitianity-preserving complex Taylor approximations of the frequency response of the correction filters. Calibration is interpreted as approximating these filters with linear combinations of base filters obtained by the proposed Taylor expansion. Known calibration techniques are reinterpreted in t... View full abstract»

• ### A 0.4-V Supply Curvature-Corrected Reference Generator With 84.5-ppm/°C Average Temperature Coefficient Within −40 °C to 130 °C

Publication Year: 2017, Page(s):362 - 366
| | PDF (971 KB)

This brief describes a low-power current-mode voltage reference based on subthreshold transistors. A novel circuit configuration together with a high-order temperature compensation scheme allow this voltage reference to operate with a supply voltage down to 0.4 V over a large temperature range (from -40 °C to 130 °C). The circuit, which is fabricated with a standard 0.18-μm CM... View full abstract»

• ### Coupling-Inductor-Based Hybrid mm-Wave CMOS SPST Switch

Publication Year: 2017, Page(s):367 - 371
Cited by:  Papers (1)
| | PDF (1134 KB)

This brief presents a hybrid CMOS millimeter-wave single-pole single-throw (SPST) switch. This newly invented hybrid structure demonstrates better tradeoffs between insertion loss and isolation compared to conventional distributed structures. The performance benefits are analyzed in detail and validated by both simulation and measurement results. Additionally, the chip area is conserved by using l... View full abstract»

• ### Influence of Initial Conditions on the Fundamental Periods of LFSR-Dithered MASH Digital Delta–Sigma Modulators With Constant Inputs

Publication Year: 2017, Page(s):372 - 376
| | PDF (1417 KB)

A digital delta-sigma modulator (DDSM) with a constant input may produce a periodic output with a small fundamental period, resulting in strong tonal output behavior instead of the expected shaped white quantization noise. In practice, the problem is alleviated by dithering the DDSM. Pseudorandom dither generators based on linear feedback shift registers (LFSRs) are widely used to “break up... View full abstract»

• ### A DC-to-8.5 GHz 32 : 1 Analog Multiplexer for On-Chip Continuous-Time Probing of Single-Event Transients in a 65-nm CMOS

Publication Year: 2017, Page(s):377 - 381
| | PDF (1511 KB)

A multiplexer circuit that is capable of accessing 32 internal nodes for the continuous-time probing of signal waveforms is proposed. A chip has been fabricated with eight multiplexer instances and used in experiments for monitoring radiation-induced single-event transients in digital circuits. Pulses with a width of less than 100 ps and pulses over 1 V in height were observed for 230-MeV particle... View full abstract»

• ### Lee's Rule Extended

Publication Year: 2017, Page(s):382 - 386
| | PDF (655 KB)

The initial step of designing a delta-sigma data converter is typically generating a noise transfer function (NTF) based on a rule of thumb such as Lee's famous rule for single-bit converters. As known, rules of such nature are merely suggestive and should be treated as an educated guess. This brief proposes a novel design rule based on optimizing NTFs to a fixed pair of norm-based metrics. Throug... View full abstract»

• ### A Two-Parameter Calibration Technique Tracking Temperature Variations for Current Source Mismatch

Publication Year: 2017, Page(s):387 - 391
| | PDF (821 KB)

This brief presents a foreground calibration technique for current source mismatch that is insensitive to temperature variations. Two calibration digital-to-analog converters (CAL DACs) provide correction currents to compensate two current source mismatch components caused by the threshold voltage mismatch and the current factor mismatch. Each CAL DAC has the same temperature dependence as its cor... View full abstract»

• ### Fully Integrated, 100-mV Minimum Input Voltage Converter With Gate-Boosted Charge Pump Kick-Started by LC Oscillator for Energy Harvesting

Publication Year: 2017, Page(s):392 - 396
| | PDF (959 KB) | HTML

A fully integrated step-up dc-dc converter for energy harvesting applications is presented. A minimum start-up voltage of 100 mV is achieved by the start-up mechanism based on an LC oscillator (LCO). Conventional voltage converters with the LCO-based start-up mechanism provide a significantly low conversion efficiency of around 1%. To overcome this drawback, the following two circuit techniques ar... View full abstract»

• Circuits and Systems for Communications
• ### A 2.3-mW 0.01-mm $^{\text{2}}$ 1.25-GHz Quadrature Signal Corrector With 1.1-ps Error for Mobile DRAM Interface in 65-nm CMOS

Publication Year: 2017, Page(s):397 - 401
| | PDF (1694 KB)

In this brief, we propose a quadrature signal corrector for a low-power DDR4 mobile DRAM interface. In order to eliminate the phase imbalance among quadrature signals, the proposed architecture employs digitally controlled delay lines in a shared digital feedback loop with a time-multiplexed loop filter so as to minimize the effect of circuit mismatch that hampers the phase accuracy. A self-calibr... View full abstract»

• ### A High-Linearity Wideband Common-Gate LNA With a Differential Active Inductor

Publication Year: 2017, Page(s):402 - 406
Cited by:  Papers (1)
| | PDF (879 KB)

A capacitor cross-coupled (CCC) wideband commongate low-noise amplifier (CGLNA) with improved linearity and frequency response is presented. A novel differential active inductor (AI) is designed to improve the in-band gain flatness and highfrequency gain using the gate-inductive gain-peaking technique. The AI prevents the small-signal current flowing to the ground through the gate-drain capacitors... View full abstract»

• ### Cascade Structure of Narrow Equiripple Bandpass FIR Filters

Publication Year: 2017, Page(s):407 - 411
| | PDF (1760 KB)

This brief introduces a novel closed-form method for a robust evaluation of partial impulse responses in a cascade structure of narrow equiripple (ER) bandpass finite-impulse-response filters. The approach presented here is based on a generating polynomial for an ER approximation. The importance of the method is seen in its inherent robustness, which significantly outperforms the existing numerica... View full abstract»

• Computer Aided Design and Electronic Design Automation
• ### A Multiobjective Cooptimization of Buffer and Wire Sizes in High-Performance Clock Trees

Publication Year: 2017, Page(s):412 - 416
| | PDF (462 KB)

Clock buffer and wire sizing are intertwined problems that also greatly impact power consumption and skew in clock trees. Due to their complexity, they are often solved separately, leading to suboptimal solutions. In this brief, we propose a new formulation for cooptimization of buffer and wire sizes for high-performance clock trees. Using the proposed cooptimization of buffer and wire sizes, we a... View full abstract»

• ### Disturbance-Observer-Based Robust Synchronization Control for a Class of Fractional-Order Chaotic Systems

Publication Year: 2017, Page(s):417 - 421
| | PDF (312 KB)

This brief studies the synchronization control for the fractional-order chaotic system subject to input saturation and external unknown disturbances. To handle unknown disturbances, a disturbance observer is designed for the fractional-order chaotic system. A disturbance-observer-based synchronization control scheme is then developed. Under the synchronization control, the asymptotically convergen... View full abstract»

• ### Dynamic Load Balancing and Reactive Power Compensation Switch Embedded in Power Meters

Publication Year: 2017, Page(s):422 - 426
| | PDF (881 KB)

This brief proposes a dynamic intelligent load balancing and reactive power compensation switch plugin for power meters and a smart scalable system architecture applicable as an add-on to the existing power distribution networks. The load-balancing module will improve the load balance in a network and thus decrease power losses, whereas the distributed reactive power compensator will decrease the ... View full abstract»

• Control Theory and Systems
• ### A Robust Repetitive-Control Design for a Class of Uncertain Stochastic Dynamical Systems

Publication Year: 2017, Page(s):427 - 431
| | PDF (665 KB)

In this brief, we study the problem of output tracking for continuous-time stochastic dynamical systems with parametric uncertainties and aperiodic disturbances by using a modified repetitive controller (MRC). More precisely, the MRC is obtained based on the equivalent input disturbance (EID) technique such that the closed-loop modified repetitive-control system is asymptotically stable in the pre... View full abstract»

• ### Improved High-Order-Reset-Element Model Based on Circuit Analysis

Publication Year: 2017, Page(s):432 - 436
| | PDF (729 KB)

In this brief, a generalized first-order reset element (GFORE) is first introduced, and its reset model is established based on circuit analysis. Then, a new class of models for the high-order reset element (HORE) is established by connecting several GFOREs and, defining a proper flow set and jump sets, the proposed model is more appropriate for describing the behavior of HORE than existing ones. ... View full abstract»

• ### High-Performance Low-Area Video Up-Scaling Architecture for 4-K UHD Video

Publication Year: 2017, Page(s):437 - 441
| | PDF (1253 KB)

A new algorithm and its hardware architecture are presented to up-scale high-definition (HD) and full-HD video streams to 4-K ultra-HD video streams in real time. The Lagrange interpolation is employed, as it provides high estimation accuracy and hardware-friendly properties. To enhance the accuracy further, the pixels at the edge regions are specially processed by employing an image-sharpening te... View full abstract»

• Digital Circuits and Systems and VLSI
• ### A Low-Voltage SRAM Sense Amplifier With Offset Cancelling Using Digitized Multiple Body Biasing

Publication Year: 2017, Page(s):442 - 446
| | PDF (1128 KB)

With continued CMOS technology scaling down, transistors exhibit higher degrees of variation and mismatch, resulting in a larger offset voltage. A large offset voltage will enlarge bitline swing, increasing dynamic power consumption during a read operation and degrading the sensing decision correct rate and operation speed. Thus, the offset voltage is the most critical metric for static random acc... View full abstract»

• ### An FPGA-Based Unscented Kalman Filter for System-On-Chip Applications

Publication Year: 2017, Page(s):447 - 451
| | PDF (425 KB)

The demand for fast and accurate state estimation in embedded systems has been increasing lately, due at least in part to mobile robotics such as an unmanned aerial vehicle (UAV). The desire to maintain high performance but with compact form factors leads to implementation issues, particularly with more complex systems. A hardware-based approach using field-programmable gate arrays may be able to ... View full abstract»

• ### An Improved DCM-Based Tunable True Random Number Generator for Xilinx FPGA

Publication Year: 2017, Page(s):452 - 456
| | PDF (1081 KB)

True random number generators (TRNGs) play a very important role in modern cryptographic systems. Field-programmable gate arrays (FPGAs) form an ideal platform for hardware implementations of many of these security algorithms. In this brief, we present a highly efficient and tunable TRNG based on the principle of beat frequency detection, specifically for Xilinx-FPGA-based applications. The main a... View full abstract»

• ### An Energy-Efficient Speech-Extraction Processor for Robust User Speech Recognition in Mobile Head-Mounted Display Systems

Publication Year: 2017, Page(s):457 - 461
| | PDF (1529 KB)

An energy-efficient speech extraction (SE) processor is proposed for robust user speech recognition (SR) in head-mounted display (HMD) systems. User SE is essential for robust user SR in a noisy environment. For the low-latency SE, the FastSE algorithm is proposed to overcome the time-consuming constrained-independent-component-analysis-based user speech selection process, which results in <; 2... View full abstract»

• Nonlinear Circuits and Systems
• ### Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation

Publication Year: 2017, Page(s):462 - 466
| | PDF (1581 KB)

Remarkable hardware robustness of deep learning (DL) is revealed by error injection analyses performed using a custom hardware model implementing parallelized restricted Boltzmann machines (RBMs). RBMs in deep belief networks demonstrate robustness against memory errors during and after learning. Fine-tuning significantly affects the recovery of accuracy for static errors injected to the structura... View full abstract»

• ### Heterogeneous Strategy Particle Swarm Optimization

Publication Year: 2017, Page(s):467 - 471
Cited by:  Papers (5)
| | PDF (2360 KB)

Particle swarm optimization (PSO) is a widely recognized optimization algorithm inspired by social swarm. In this brief, we present a heterogeneous strategy PSO (HSPSO), in which a proportion of particles adopts a fully informed strategy to enhance the converging speed while the rest is singly informed to maintain the diversity. Our extensive numerical experiments show that the HSPSO algorithm is ... View full abstract»

## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org