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# IEEE Transactions on Circuits and Systems II: Express Briefs

## Filter Results

Displaying Results 1 - 25 of 31

Publication Year: 2017, Page(s):C1 - C4
| PDF (46 KB)
• ### IEEE Transactions on Circuits and Systems—II:Express Briefs publication information

Publication Year: 2017, Page(s): C2
| PDF (64 KB)
• ### Design Considerations of Charge Pump for Antenna Switch Controller With SOI CMOS Technology

Publication Year: 2017, Page(s):229 - 233
| | PDF (1244 KB) | HTML

An enhanced charge pump for the antenna switch controller using the silicon-on-insulator (SOI) CMOS technology is presented in this brief. The pseudo cross-coupled technique is proposed to reduce parasitic capacitances at charging/discharging nodes through charge transferring paths, which improves the current drive capability and provides better accuracy of the output voltage. Furthermore, the cod... View full abstract»

• ### High-Efficiency E-Band Power Amplifiers and Transmitter Using Gate Capacitance Linearization in a 65-nm CMOS Process

Publication Year: 2017, Page(s):234 - 238
| | PDF (1910 KB) | HTML

This brief presents a new design technique for high-efficiency CMOS millimeter-wave power amplifiers (PAs) and the implementations of a two-stage moderate-power PA, a three-stage high-power PA, and a transmitter all working over 68-78 GHz. The proposed PAs adopt nMOS capacitors connected at the gates of the transistors of the last one or two amplifying stages to compensate for the gate capacitance... View full abstract»

• ### Analysis of Millimeter-Wave LC Oscillators Based on Two-Port Network Theory

Publication Year: 2017, Page(s):239 - 243
| | PDF (564 KB) | HTML

In this brief, a cross-coupled oscillator is analyzed based on the two-port network theory and the Y- parameter model for a transistor. Contrary to the previous works, the proposed analysis shows that LC cross-coupled oscillators have an additional and higher pure imaginary natural frequency at which the circuit cannot oscillate. The analysis investigates the sufficient condition at which the circ... View full abstract»

• Analog and Mixed Mode Circuits and Systems
• ### A 0.95-mW 6-b 700-MS/s Single-Channel Loop-Unrolled SAR ADC in 40-nm CMOS

Publication Year: 2017, Page(s):244 - 248
| | PDF (998 KB) | HTML

This brief presents a low-power and high-speed single-channel successive approximation register (SAR) analog-to-digital converter (ADC). It uses a loop-unrolled architecture with multiple comparators. Each comparator is used not only to make a comparison but also to store its output and generate an asynchronous clock to trigger the next comparator. The SAR logic is significantly simplified to incr... View full abstract»

• ### A Phase-Interpolator-Based Fractional Counter for All-Digital Fractional-N Phase-Locked Loop

Publication Year: 2017, Page(s):249 - 253
| | PDF (1593 KB) | HTML

A phase-interpolator-based fractional counter (PIFC) is proposed to reduce power consumption by replacing TDC in a ring-oscillator-based digital fractional-N phase-locked loop. A predicted-phase-interpolation method is used to calculate the integer and fractional parts of the frequency-division-ratio and to find two interpolation clocks; the prediction method gives a significant power reduction in... View full abstract»

• ### D-Band Common-Base Amplifiers With Gain Boosting and Interstage Self-Matching in 0.18- $\mu\text{m}$ SiGe HBT Technology

Publication Year: 2017, Page(s):254 - 258
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This paper presents two D-band amplifiers fabricated in a 0.18-μm SiGe heterojunction bipolar transistor process. A single-ended amplifier employs a five-stage common-base topology, and a differential amplifier combines two of the single-ended chains. To overcome the limited available gain of the given technology at D-band, a gain-boosting technique based on positive feedback is adopted for... View full abstract»

• ### Heterogeneous Multi-ASIP and NoC-Based Architecture for Adaptive Parallel TBICM-ID-SSD

Publication Year: 2017, Page(s):259 - 263
Cited by:  Papers (2)
| | PDF (1031 KB) | HTML

A novel multi-ASIP and network-on-chip (NoC) based flexible architecture for parallel iterative demapping with turbo decoding using signal space diversity (TBICM-ID-SSD) is presented in this brief. The proposed heterogeneous multi-ASIP architecture uses multiple instances of two types of application-specific instruction-set processor (ASIP): one dedicated for turbo decoding and the second for demo... View full abstract»

• Circuits and Systems for Communications
• ### Analysis of Second-Order Intermodulation in Miller Bandpass Filters

Publication Year: 2017, Page(s):264 - 268
| | PDF (397 KB) | HTML

Miller bandpass filters combine the properties of N-path circuits with the Miller effect to achieve a narrow bandwidth and high out-of-channel rejection. This brief investigates the second-order intermodulation behavior of such filters in the context of direct-conversion receivers. It is shown that the second intercept point rises by an amount equal to the circuit's out-of-channel rejection. View full abstract»

• ### A TV Receiver Front-End With Linearized LNA and Current-Summing Harmonic Rejection Mixer

Publication Year: 2017, Page(s):269 - 273
| | PDF (1773 KB) | HTML

A low-noise and highly linear wideband receiver front-end composed of the linearized low noise amplifier and current-summing harmonic rejection mixer is implemented in a 0.18-μm CMOS process for TV tuner applications. It shows a measured voltage gain (Av) of more than 34.5 dB, a noise figure of less than 3.5 dB, and a third-order input-referred intercept point (IIP3) of more than... View full abstract»

• Computer Aided Design and Electronic Design Automation
• ### Systematic Design Space Exploration of Floating-Point Expressions on FPGA

Publication Year: 2017, Page(s):274 - 278
| | PDF (1262 KB) | HTML

In this brief, we propose novel methods to systematically explore the design space of floating-point expressions on a field-programmable gate array in order to extract a nondominated set that covers the whole design space in terms of the accuracy, area, and run-time numbers. We first introduce a regular selection method that consists of two main phases: 1) generating equivalent expressions and 2) ... View full abstract»

• ### Wireless Power Transfer System With $SigmaDelta$- Modulated Transmission Power and Fast Load Response for Implantable Medical Devices

Publication Year: 2017, Page(s):279 - 283
| | PDF (1167 KB) | HTML

The Class-D power amplifier (PA) is widely used to drive the primary coil of wireless power transfer (WPT) systems. Due to coupling and loading variations, the PA is required to adjust the transmission power quickly, precisely, and efficiently. In this brief, a switching-frequency-modulation-based Sigma-Delta (ΣΔ) modulator is proposed for driving the PA with minimal hardware overhea... View full abstract»

• ### Consensus of Linear Multiagent Systems With Actuator Saturation and External Disturbances

Publication Year: 2017, Page(s):284 - 288
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This brief considers the leader-following consensus problem for linear multiagent systems with actuator saturation and external disturbances. By enlarging the contractively invariant set to estimate the domain of consensus attraction (DOCA) of the origin, this brief derives a condition to estimate the DOCA under the actuator saturation and magnitude-bounded disturbances. For the energy-bounded dis... View full abstract»

• Power Systems and Electronic Circuits
• ### An Analytical Time–Domain Expression for the Net Ripple Produced by Parallel Interleaved Converters

Publication Year: 2017, Page(s):289 - 293
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We apply modular arithmetic and Fourier series to analyze the superposition of N interleaved triangular waveforms with identical amplitudes and duty ratios. Here, interleaving refers to the condition when a collection of periodic waveforms with identical periods is uniformly phase shifted across one period. The main result is a time-domain expression that provides an exact representation of the su... View full abstract»

• ### An Efficient Zero Current Switching Control for L-Based DC–DC Converters in TEG Applications

Publication Year: 2017, Page(s):294 - 298
| | PDF (1194 KB) | HTML

This brief presents an improved zero current switching (ZCS) control for a high-gain inductor-based dc-dc converter targeting thermoelectric generator for wearable electronics. The proposed ZCS control is an all-digital circuit that utilizes a simple finite state machine and a 3-bit counter to locate the zero current point. In addition, an efficient push-pull circuit along with delay capacitance b... View full abstract»

• Control Theory and Systems
• ### Input Design-Based Compensation Control for Networked Nonlinear Systems With Random Delays and Packet Dropouts

Publication Year: 2017, Page(s):299 - 303
| | PDF (312 KB) | HTML

This brief investigates the data-based networked control problem of a class of nonlinear systems, where random network-induced delays and packet dropouts in the feedback and forward channels are considered simultaneously and further treated as random round-trip time (RTT) delays. The main contributions of this brief are as follows: 1) To actively compensate for RTT delays, a novel compensation con... View full abstract»

• ### Nonnegative Edge Quasi-Consensus of Networked Dynamical Systems

Publication Year: 2017, Page(s):304 - 308
Cited by:  Papers (2)
| | PDF (272 KB) | HTML

Differing from the existing literature on node consensus, this brief studies consensus taking place on the edges of networked dynamical systems. A distributed edge quasi-consensus protocol is developed to lead the states of all edges to converge into a bounded region. For a connected network with nonnegative initial edge states, it is proved that the edge quasi-consensus can be reached while the s... View full abstract»

• Digital Circuits and Systems and VLSI
• ### An FPGA-Based Cloud System for Massive ECG Data Analysis

Publication Year: 2017, Page(s):309 - 313
| | PDF (1244 KB) | HTML

In this brief, we propose a stand-alone system-on-a-programmable-chip (SOPC)-based cloud system to accelerate massive electrocardiogram (ECG) data analysis. The proposed system tightly couples network I/O handling hardware to data processing pipelines in a single field-programmable gate array (FPGA), offloading both networking operations and ECG data analysis. In this system, we first propose a ma... View full abstract»

• ### Register-Less NULL Convention Logic

Publication Year: 2017, Page(s):314 - 318
| | PDF (1073 KB) | HTML

NULL Convention Logic (NCL) is a promising design paradigm for constructing low-power robust asynchronous circuits. The conventional NCL paradigm requires pipeline registers for separating two neighboring logic blocks, and those registers can account for up to 35% of the overall power consumption of the NCL circuit. This brief presents the Register-Less NCL (RL-NCL) design paradigm, which achieves... View full abstract»

• ### HUB Floating Point for Improving FPGA Implementations of DSP Applications

Publication Year: 2017, Page(s):319 - 323
| | PDF (1114 KB) | HTML

The increasing complexity of new digital signal processing (DSP) applications is forcing the use of floating point (FP) numbers in their hardware implementations. In this brief, we investigate the advantages of using half-unit biased (HUB) formats to implement these FP applications on field-programmable gate arrays (FPGAs). These new FP formats allow for the effective elimination of the rounding l... View full abstract»

• Digital Circuits and Systems and VLSI
• ### Aging Benefits in Nanometer CMOS Designs

Publication Year: 2017, Page(s):324 - 328
| | PDF (1370 KB) | HTML

In this brief, we show that bias temperature instability (BTI) aging of MOS transistors, together with its detrimental effect for circuit performance and lifetime, presents considerable benefits for static power consumption due to subthreshold leakage current reduction. Indeed, static power reduces considerably, making CMOS circuits more energy efficient over time. Static power reduction depends o... View full abstract»

• Nonlinear Circuits and Systems
• ### An Integrated Dual Entropy Core True Random Number Generator

Publication Year: 2017, Page(s):329 - 333
Cited by:  Papers (1)
| | PDF (1047 KB) | HTML

In this brief, we present the first integrated circuit implementation of our previously proposed dual entropy core true-random-number-generator architecture, which is designed following a novel parameter variation-aware approach. A prototype integrated circuit has been fabricated in 180-nm CMOS technology. The prototype chip achieved a 35-Mbps throughput with an approximately 33-pJ/b energy effici... View full abstract»

• ### Stochastic Stability Condition for the Extended Kalman Filter With Intermittent Observations

Publication Year: 2017, Page(s):334 - 338
Cited by:  Papers (1)
| | PDF (316 KB) | HTML

In order to tackle the intermittent observations, this brief addresses the stochastic stability problem of the extended Kalman filter by means of analyzing the prediction error covariance matrix (PECM) and the estimation error performance of the estimator. With the transmitted measurement output of the filter modeled as a Bernoulli process, the existence of a crucial arrival rate is proved such th... View full abstract»

• ### A Novel Four-Dimensional Hyperchaotic Four-Wing System With a Saddle–Focus Equilibrium

Publication Year: 2017, Page(s):339 - 343
| | PDF (903 KB) | HTML

A novel 4-D hyperchaotic four-wing system with a saddle-focus equilibrium is introduced in this brief. The qualitative analysis of the proposed system confirms its complex dynamic behavior, which is studied by using well-known numerical tools of nonlinear theory, such as the bifurcation diagram, Lyapunov exponents, Poincaré maps, and phase portraits. Furthermore, the novel hyperchaotic sys... View full abstract»

## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org