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IEEE Design & Test

Issue 2 • April 2017

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Displaying Results 1 - 23 of 23
  • Front Cover

    Publication Year: 2017, Page(s): C1
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  • Cover 2

    Publication Year: 2017, Page(s): C2
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  • IEEE Design&Test publication information

    Publication Year: 2017, Page(s): 1
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  • Table of Contents

    Publication Year: 2017, Page(s):2 - 3
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  • Power Density

    Publication Year: 2017, Page(s): 4
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  • Guest Editors’ Introduction: Computing in the Dark Silicon Era

    Publication Year: 2017, Page(s):5 - 7
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  • Computing in the Dark Silicon Era: Current Trends and Research Challenges

    Publication Year: 2017, Page(s):8 - 23
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3310 KB) | HTML iconHTML

    Power density has become the major constraint for many on-chip designs. As an introduction to the Special Issue on Dark Silicon, the authors provide the newest trends and a survey on the topic that has valuable information for novices and experts alike. View full abstract»

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  • Near Threshold Voltage (NTV) Computing: Computing in the Dark Silicon Era

    Publication Year: 2017, Page(s):24 - 30
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1474 KB) | HTML iconHTML

    Near-threshold computing has emerged as an attractive paradigm for energy efficiency. This article discusses challenges and opportunities for designing complex system on chips that can operate in the near-threshold voltage range. Evaluation for 32- and 22-nm test chips is presented. View full abstract»

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  • Impact of FinFET on Near-Threshold Voltage Scalability

    Publication Year: 2017, Page(s):31 - 38
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (915 KB) | HTML iconHTML

    Near-threshold operations provide a powerful knob for improving energy efficiency and alleviating on-chip power densities. This article explores the impact of newest FinFET CMOS technologies (from 40 to 7 nm) on near-threshold computing in terms of performance and energy efficiency. View full abstract»

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  • Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era

    Publication Year: 2017, Page(s):39 - 50
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1148 KB) | HTML iconHTML

    Unlike traditional dark silicon works that attack the computing logic, this article puts a focus on the memory part, which dissipates most of the energy for memory-bound CPU applications. This article discusses the dark memory state and present Pareto curves for compute units, accelerators, and on-chip memory, and motivates the need for HW/SW codesign for parallelism and locality. View full abstract»

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  • Can Dark Silicon Be Exploited to Prolong System Lifetime?

    Publication Year: 2017, Page(s):51 - 59
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2476 KB) | HTML iconHTML

    Besides stringent power and thermal constraints, a dark silicon chip is also subjected to various reliability threats. This article illustrates how the dark silicon can be exploited to improve the chip's lifetime through efficient utilization of computational resources and power budget, while still performing in a similar way. -Muhammad Shafique, Vienna University of Technology. View full abstract»

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  • AxBench: A Multiplatform Benchmark Suite for Approximate Computing

    Publication Year: 2017, Page(s):60 - 68
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1106 KB) | HTML iconHTML

    Approximate computing is claimed to be a powerful knob for alleviating the peak power and energy-efficiency issues. However, providing a consistent benchmark suit with diverse applications amenable to approximate computing is crucial to ensure fair and reproducible comparisons. This article makes an important attempt toward it in the form of the AxBench suite, which contains applications for CPUs,... View full abstract»

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  • Controller Architecture for Low-Power, Low-Latency DRAM With Built-in Cache

    Publication Year: 2017, Page(s):69 - 78
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1487 KB) | HTML iconHTML

    Memory wall is a critical issue for many today's electronic systems. Tiered latency DRAM with asymmetric bit lines was proposed to optimize the power and latency. This paper proposes a controller architecture for the tiered latency DRAM in which the small array is operated like a cache. View full abstract»

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  • A Fully Automated and Configurable Cost-Aware Framework for Adaptive Functional Diagnosis

    Publication Year: 2017, Page(s):79 - 86
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (225 KB) | HTML iconHTML

    Editor's note: This paper presents an approach that enables users to tune the board diagnosis process in order to trade off the level of accuracy for savings in the diagnosis cost. View full abstract»

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  • The Physics of Event-Driven IoT Systems

    Publication Year: 2017, Page(s):87 - 90
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (102 KB) | HTML iconHTML

    Internet of Things (IoT) systems will require the installation and operation of huge numbers of sensors and processing nodes. Self-powered, energy- scavenging IoT devices would reduce the installation and operational cost of these systems. But energy scavenging faces basic limits on the amount of power that can be drawn from the environment, and IoT devices exhibit similar lower bounds on the amou... View full abstract»

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  • IEEE Collbratec

    Publication Year: 2017, Page(s): 91
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  • Highlights of ICCAD 2016

    Publication Year: 2017, Page(s):92 - 93
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  • Edward J. McCluskey 1929-2016

    Publication Year: 2017, Page(s):94 - 98
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  • TTTC News

    Publication Year: 2017, Page(s):99 - 101
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  • Call for Contributions Special Issue on Time-Critical Systems Design

    Publication Year: 2017, Page(s):102 - 103
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  • Dark Silicon, Antiparallelism, and Too Much Work

    Publication Year: 2017, Page(s): 104
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  • Cover 3

    Publication Year: 2017, Page(s): C3
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  • Cover 4

    Publication Year: 2017, Page(s): C4
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Aims & Scope

IEEE Design & Test offers original works describing the models, methods and tools used to design and test microelectronic systems from devices and circuits to complete systems-on-chip and embedded software. The magazine focuses on current and near-future practice, and includes tutorials, how-to articles, and real-world case studies. The magazine seeks to bring to its readers not only important technology advances but also technology leaders, their perspectives through its columns, interviews and roundtable discussions. Topics include semiconductor IC design, semiconductor intellectual property blocks, design, verification and test technology, design for manufacturing and yield, embedded software and systems, low-power and energy efficient design, electronic design automation tools, practical technology, and standards.  

It was published as IEEE Design & Test of Computers between 1984 and 2012.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Joerg Henkel
Chair for Embedded Systems (CES)
Karlsruhe Institute of Technology (KIT)