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Computers and Digital Techniques, IEE Proceedings -

Issue 6 • Date Nov 1994

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Displaying Results 1 - 15 of 15
  • KGPMAP:library-based technology-mapping technique for antifuse based FPGAs

    Publication Year: 1994 , Page(s): 361 - 368
    Cited by:  Papers (5)  |  Patents (1)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (628 KB)  

    Owing to their high degree of flexibility and low design-turnaround time, field-programmable-gate-array (FPGA) based designs are becoming very popular. With the availability of different types of FPGA, the need of a unified approach for logic-block-independent technology mapping is being felt increasingly. The paper presents a new approach to efficient realisation of a given combinational function... View full abstract»

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  • Guiding instruction scheduling with synchronisation markers on a superscalar based multiprocessor

    Publication Year: 1994 , Page(s): 398 - 404
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (532 KB)  

    Exploiting loop parallelism is an important way to enhance system performance. For loop-carried dependence, the original DO loop is converted into a DOACROSS loop to function concurrently. In general, synchronisation operations are inserted to maintain order dependence during parallel execution. For each processor in a shared memory multiprocessor, if the executing sequence is the same as the orig... View full abstract»

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  • Concurrent-error detection in high-speed carry-free dividers

    Publication Year: 1994 , Page(s): 356 - 360
    Cited by:  Papers (3)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (332 KB)  

    Rapid advancements in technology demand innovative computation algorithms and hardware structures to achieve high performance. High-speed dividers are commonly designed using SRT division methods. Recently, a high-speed carry-free divider design using redundant binary representation has been presented. Based on the carry-free division algorithm and a more general cell-fault model instead of stuck-... View full abstract»

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  • Multi-exponentiation [cryptographic protocols]

    Publication Year: 1994 , Page(s): 325 - 326
    Cited by:  Papers (7)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (132 KB)  

    In several cryptographic protocols the product of a small number of exponentiations is required, but the separate exponentiation results are not needed. A simultaneous exponentiation algorithm that takes advantage of this situation and that is substantially faster than the ordinary approach using separate exponentiations is presented View full abstract»

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  • VLSI structures for bit-serial modular multiplication using basis conversion

    Publication Year: 1994 , Page(s): 381 - 390
    Cited by:  Papers (2)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (612 KB)  

    This paper proposes design techniques for the efficient VLSI implementation of bit-serial multiplication over a modulus. These techniques reduce multiplication into simple cyclic shifts, where the number representation of the data is chosen appropriately. This representation will, in general, be highly redundant, implying a relatively poor throughput for the multiplier. It is then shown how, by sp... View full abstract»

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  • Division unit with Newton-Raphson approximation and digit-by-digit refinement of the quotient

    Publication Year: 1994 , Page(s): 317 - 324
    Cited by:  Papers (5)  |  Patents (3)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (604 KB)  

    The advantages of the convergence with the square of the Newton-Raphson method are combined with the precision characteristics of digit-by-digit algorithms to obtain units for fast division that satisfy the IEEE 754 floating point standard requirements. A general design methodology that leads to a class of alternative architectures providing interesting performances for division is presented, toge... View full abstract»

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  • Constant-division algorithms

    Publication Year: 1994 , Page(s): 334 - 340
    Cited by:  Papers (5)  |  Patents (2)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (472 KB)  

    There exist many types of special-purpose systems that require rapid and repeated division by a set of known constant divisors. Numerous solutions have been proposed in response to the deficiencies of the conventional division algorithms for applications which involve repeated divisions by known constants. Six approaches are reviewed in detail and their relationships are shown by reducing them to ... View full abstract»

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  • Implementation of dynamic look-up tables

    Publication Year: 1994 , Page(s): 391 - 397
    Cited by:  Papers (1)  |  Patents (4)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (496 KB)  

    Look-up tables are used extensively in telecommunications networks in such areas as multiplexing, switching, routing and reassembly. There are also many applications involving look-up tables outside the field of telecommunications, such as electronic dictionaries and database search algorithms. Essentially, look-up tables map sets of input numbers onto arbitrary sets of output numbers. The paper d... View full abstract»

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  • Stride: a tool for formal interactive system synthesis

    Publication Year: 1994 , Page(s): 347 - 355
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (500 KB)  

    Transformational synthesis is the process of generating a hardware implementation from an initial behavioural description, by repeatedly applying transformations to the behavioural descriptions until a satisfactory implementation can be generated. Although it is essential to verify the correctness of the applied transformations, it is also very important to present the changes to the designer in a... View full abstract»

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  • Performance of scheduling algorithms for channel reservation

    Publication Year: 1994 , Page(s): 341 - 346
    Cited by:  Papers (1)  |  Patents (4)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (396 KB)  

    The performance of scheduling algorithms for a reservation system is investigated. In this system, a user request is characterised by its start time, resource requirement and holding time. Of interest are scheduling algorithms to handle user requests in a loss system where resource requirements may vary. A Markov decision process formulation is used to obtain the optimal scheduling decisions. Two ... View full abstract»

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  • Minimisation of fixed-polarity AND/XOR canonical networks

    Publication Year: 1994 , Page(s): 369 - 374
    Cited by:  Papers (6)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (436 KB)  

    A method for extracting the cubes of the generalised Reed-Muller (GRM) form of a Boolean function with a given polarity is presented. The method does not require exponential space and time complexity and it achieves the lower-bound time complexity. The proof of the method's correctness constitutes the first half of the paper. Also, a separate heuristic algorithm to find the optimal polarity that r... View full abstract»

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  • Radix digit-serial pipelined divider/square-root architecture

    Publication Year: 1994 , Page(s): 375 - 380
    Cited by:  Papers (2)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (400 KB)  

    The paper presents a new digit-serial architecture for division and square-root which can be pipelined to the bit level to achieve high throughput. The architecture is different from the existing divider/square-root architectures in that it is based on the radix-2n algorithm. As a result, any type of adder can be used in the proposed digit-serial controlled add/subtract basic cell. The ... View full abstract»

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  • Parallel design of arithmetic coding

    Publication Year: 1994 , Page(s): 327 - 333
    Cited by:  Papers (10)  |  Patents (1)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (500 KB)  

    The paper presents a parallel algorithm design for real-time implementation of arithmetic coding. The implementation comprises a parallel-processing array arranged in a tree structure. Within each cycle, a group of input symbols can be encoded. This increases the arithmetic coding speed substantially. Details of a fixed-precision algorithm design, its implementation and simulation of its performan... View full abstract»

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  • General area router based on planning techniques

    Publication Year: 1994 , Page(s): 413 - 420
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (596 KB)  

    A general area router (GEAR) based on the planning approach is proposed and implemented. Two meta-planning techniques, graceful retreat and least impact, are used to manage the selection of net segments and the assignment of track resources. Apart from the novel application of these planning techniques, we have also consolidated many effective routing heuristics into GEAR so that it is able to sol... View full abstract»

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  • Petri-net-based algorithms for parallel-controller synthesis

    Publication Year: 1994 , Page(s): 405 - 412
    Cited by:  Papers (12)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (540 KB)  

    The paper presents new algorithms for the synthesis of parallel controllers which operate on a Petri net. This net is first simplified by reduction, then coloured and finally used to generate a state assignment with which the controller can be synthetised. The new concept of using colours for detecting and representing concurrency within the Petri net is presented. Experimental results show that t... View full abstract»

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