# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 25

Publication Year: 2017, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I:Regular Papers publication information

Publication Year: 2017, Page(s): C2
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• ### Processes of AM-PM Distortion in Large-Signal Single-FET Amplifiers

Publication Year: 2017, Page(s):245 - 260
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Using an appropriate formulation of field-effect transistor (FET) current as a nonlinear function of terminal voltages, and a simplified model of gain compression in common source amplifiers, we are able to identify four principal sources of amplitude-to-phase (AM-PM) distortion. A new analysis shows the varactor effect of gate-source capacitance on AM-PM distortion, and the changing Miller-multip... View full abstract»

• ### A Study of Operating Condition and Design Methods to Achieve the Upper Limit of Power Gain in Amplifiers at Near- $f_{max}$ Frequencies

Publication Year: 2017, Page(s):261 - 271
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A study of operating condition and design methods is presented that enables the amplifiers to achieve the upper limit of their power gain at frequencies close to the device fmax. Using the gain-plane approach, the necessary and sufficient conditions to achieve this theoretical upper limit are obtained and the results are analytically verified. As will be demonstrated, the maximum power ... View full abstract»

• ### A MPPT Circuit With 25 $\mu\text{W}$ Power Consumption and 99.7% Tracking Efficiency for PV Systems

Publication Year: 2017, Page(s):272 - 282
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A Maximum Power Point Tracking (MPPT) circuit for a 0.7-W photovoltaic (PV) system is proposed. The circuit employs a modified hill-climbing algorithm based on a 3-points comparison instead of the traditional 2-points comparison. The adopted algorithm simplifies the detection of the Maximum Power Point (MPP) and enables the implementation of a periodic sleep-mode to reduce the overall power consum... View full abstract»

• ### A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC

Publication Year: 2017, Page(s):283 - 295
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Generation of low jitter, high frequency clock from a low frequency reference clock using classical analog phaselocked loops (PLLs) requires large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by quantization error. Specifically, their deterministic jitter (DJ), which is proportional to the loop update rate be... View full abstract»

• ### Partial Dynamic Element Matching Technique for Digital-to-Analog Converters Used for Digital Harmonic-Cancelling Sine-Wave Synthesis

Publication Year: 2017, Page(s):296 - 309
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Digital harmonic-cancelling sine-wave synthesizers (DHSSs) use a 47 year old concept, recently revived as a power and area efficient solution for on-chip sine-wave synthesis. The operation of a DHSS involves amplitude scaling and summing a set of square-waves to produce a sampled sine-wave. The circuit which performs the scaling and summing operation is referred to as the harmonic-cancelling digit... View full abstract»

• ### A 33fJ/Step SAR Capacitance-to-Digital Converter Using a Chain of Inverter-Based Amplifiers

Publication Year: 2017, Page(s):310 - 321
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A 12 - bit energy-efficient capacitive sensor interface circuit that fully relies on capacitance-domain successive approximation (SAR) technique is presented. Analysis shows that for SAR capacitance-to-digital converter (CDC) comparator offset voltage will result in parasitic-dependent conversion errors, which necessitates using an offset cancellation technique. Based on the presented analysis, a ... View full abstract»

• ### Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC

Publication Year: 2017, Page(s):322 - 332
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This paper proposes a linearity calibration algorithm of a capacitive digital-to-analog converter (CDAC) for successive approximation register (SAR) analog-to-digital converters (ADCs) based on a normalized-full-scale of the DAC. Since the capacitor weight errors are represented as the difference between the real and ideal weights with respect to the normalized-full-scale, the calibrated digital r... View full abstract»

• ### Introducing Suspendance Analysis

Publication Year: 2017, Page(s):333 - 346
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Suspendance analysis is based on determinant expansion and is an effective tool for calculating node admittances. The node admittance is equal to the ratio of the suspendance obtained when the node is open to the suspendance obtained when the node is shorted. Suspendance is expressed in terms of circuit admittances and transadmittances and is calculated by shorting passive circuit components based... View full abstract»

• ### Time-Domain Analysis of Passive Mixer Impedance: A Switched-Capacitor Approach

Publication Year: 2017, Page(s):347 - 359
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Passive mixers have become an essential component of SAW-less communication receivers in the last few years, this has encouraged many researchers to study their impedance characteristics. When observed from the input radio frequency (RF) port of the passive mixer, the impedance exhibits bandpass filtering characteristics centered around the frequency of the local oscillator (LO) signal. The theory... View full abstract»

• ### A 1.2V-to-0.4V 3.2GHz-to-14.3MHz Power-Efficient 3-Port Register File in 65-nm CMOS

Publication Year: 2017, Page(s):360 - 372
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This paper presents a 44.2-mW 3.2-GHz 3-port register file (RF) that demonstrates measured operation from 1.2 V down to 0.4 V. The 32-entry× 32-bit/word 2-read/1-write RF is fabricated in TSMC 65-nm low-power low threshold voltage (low-Vt) CMOS process. A four-transistor read port is presented that permits the design of low-capacitance dynamic local bitlines (LBLs). Switching pow... View full abstract»

• ### Optimized Memristor-Based Multipliers

Publication Year: 2017, Page(s):373 - 385
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Since memristors came to the forefront of research, minimal work has explored their application to computer arithmetic. This paper proposes two memristor-based implementations of an N-bit shift-and-add multiplier, one using IMPLY operations and a second using MAD operations. The optimized IMPLY-based implementation reduces the baseline delay from 2N2 + 29N steps and 17N+3 memristors to ... View full abstract»

• ### Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division

Publication Year: 2017, Page(s):386 - 398
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Floating point division is a core arithmetic widely used in scientific and engineering applications. This paper proposed an architecture for double precision floating point division. This architecture is designed for dual-mode functionality, which can either compute on a pair of double precision operands or on two pairs of single precision operands in parallel. The architecture is based on the ser... View full abstract»

• ### Low-Latency, Low-Area, and Scalable Systolic-Like Modular Multipliers for $GF(2^{m})$ Based on Irreducible All-One Polynomials

Publication Year: 2017, Page(s):399 - 408
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In this paper, an efficient recursive formulation is suggested for systolic implementation of canonical basis finite field multiplication over GF(2m) based on irreducible AOP. We have derived a recursive algorithm for the multiplication, and used that to design a regular and localized bit-level dependence graph (DG) for systolic computation. The bit-level regular DG is converted into a ... View full abstract»

• ### Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction

Publication Year: 2017, Page(s):409 - 418
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In this paper, we describe an optimization for binary radix-16 (modified) Booth recoded multipliers to reduce the maximum height of the partial product columns to [n/4] for n = 64-bit unsigned operands. This is in contrast to the conventional maximum height of [(n + 1)/4]. Therefore, a reduction of one unit in the maximum height is achieved. This reduction may add flexibility during the design of ... View full abstract»

• ### Lattice Structure Realization for The Design of 2-D Digital Allpass Filters With General Causality

Publication Year: 2017, Page(s):419 - 431
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This paper presents a lattice structure for the realization of two-dimensional (2-D) recursive digital allpass filters (DAFs) with general causality. We employ four basic lattice sections to realize 2-D recursive DAFs with wedge-shaped coefficient support region like a nonsymmetric half-plane (NSHP) support region. The theory and transfer functions of the realized 2-D lattice DAFs are derived. Som... View full abstract»

• ### A General Theory of Phase Noise in Transconductor-Based Harmonic Oscillators

Publication Year: 2017, Page(s):432 - 445
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We present a rigorous phase noise analysis of a generic harmonic oscillator where the active core can be modeled as a transconductor. Phase noise equations are derived without any specific assumption on the nature of the resonator in the oscillator; furthermore, we provide closed-form 1/f2 phase noise equations when the resonator consists of an arbitrary number of cascaded LC tanks, eac... View full abstract»

• ### A Flexible Geometric Mean Decomposition Processor for MIMO Communication Systems

Publication Year: 2017, Page(s):446 - 456
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This paper presents a geometric-mean-decomposition (GMD) processor for multiple-input multiple-output (MIMO) communication systems. The proposed GMD processor has a flexible architecture that supports channel matrices of arbitrary dimensions. A complex-valued bi-diagonalization is proposed at the preprocessing stage, which substantially reduces the overall hardware complexity. The proposed GMD pro... View full abstract»

• ### Optimization Techniques for the Efficient Implementation of High-Rate Layered QC-LDPC Decoders

Publication Year: 2017, Page(s):457 - 470
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For high-rate low-density parity-check (LDPC) codes, layered decoding processing can be reordered such that the first-in-first-out (FIFO) buffer that stores variable-to-check (V2C) messages is not needed and, hence, the memory area can be minimized, but at the cost of increased data dependency. This paper presents three techniques that can be used to implement an efficient reordered layered decode... View full abstract»

• ### Analysis and Design of Power Harvesting Circuits for Ultra-Low Power Applications

Publication Year: 2017, Page(s):471 - 479
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This paper presents an analytical model for power harvester circuits used in Ultra-low power applications. Assuming that the MOS devices of the circuit fully operate in the Sub-threshold regime in both forward and reverse regions, closed-form equations for important properties of the rectifier circuit such as output voltage, efficiency and input resistance are derived. The model includes the effec... View full abstract»

• ### Generalized High Step-Up DC-DC Boost-Based Converter With Gain Cell

Publication Year: 2017, Page(s):480 - 493
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High step-up conversion is an indispensable feature for the power processing of low voltage renewable sources in grid-connected systems. Motivated by this necessity, this paper presents a study on non-isolated dc-dc converters based on the conventional Boost converter that can provide such feature with high efficiency. By the topological variation and gain cell concepts, it is demonstrated that th... View full abstract»

• ### Wireless Power Transfer With Three-Ports Networks: Optimal Analytical Solutions

Publication Year: 2017, Page(s):494 - 503
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A wireless transfer link between three magnetically coupled resonators has been considered. Two different configurations have been investigated. In one case a single transmitter and two receivers are present. In the other case two transmitters and a single receiver are employed. For each case optimal analytical solutions for the load values that maximize the power delivered to the load(s) and the ... View full abstract»

• ### IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors

Publication Year: 2017, Page(s): 504
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• ### IEEE Circuits and Systems Society Information

Publication Year: 2017, Page(s): C3
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## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK