IEEE Electron Device Letters

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Publication Year: 2017, Page(s):C1 - C4
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• IEEE Electron Device Letters

Publication Year: 2017, Page(s): C2
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• Evidence of Supercoupling Effect in Ultrathin Silicon Layers Using a Four-Gate MOSFET

Publication Year: 2017, Page(s):157 - 159
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The supercoupling effect is demonstrated experimentally by monitoring the electron and hole currents in a field-effect transistor provided with p+ and n+ contacts. According to the polarity of the voltage applied to the front and back gates, only electrons or holes can be detected in 7-nm thick silicon layers. Thicker layers are not affected by supercoupling and can accommoda... View full abstract»

• Hot-Carrier Degradation Modeling of Decananometer nMOSFETs Using the Drift-Diffusion Approach

Publication Year: 2017, Page(s):160 - 163
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We extend our previously suggested drift-diffusion (DD)-based hot-carrier degradation model to the case of decananometer transistors. Special attention is paid to the effect of electron-electron scattering, which populates the high energy tail of the carrier distribution function, by using a rate balance equation. We compare the results of the DD-based model with the results obtained from a spheri... View full abstract»

• Influence of Intercell Trapped Charge on Vertical NAND Flash Memory

Publication Year: 2017, Page(s):164 - 167
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The influence of intercell trapped charge (ITC)-the charge trapped at the inter-cell nitride regions by fringe electric fields during program and erase operations-on vertical NAND (VNAND) flash memory is investigated. In addition to conventional degradation mechanisms such as tunnel oxide damage, ITC deteriorates the transconductance and read current of VNAND flash memory cells. The influence of I... View full abstract»

• Optimization of RRAM-Based Physical Unclonable Function With a Novel Differential Read-Out Method

Publication Year: 2017, Page(s):168 - 171
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RRAM-based physical unclonable function (PUF) leveraging the remarkable resistance variability has been proposed and experimentally demonstrated on a 1-kb one-transistor one-resistor array. In this letter, a novel differential read-out method is utilized to reduce the effect of resistance window degradation. The RRAM PUF reliability is optimized through a reliability-enhancement design and oxide s... View full abstract»

• A Novel Operation Scheme Enabling Easy Integration of Selector and Memory

Publication Year: 2017, Page(s):172 - 174
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In this letter, by utilizing the unique property of large hysteresis of threshold selector, a novel operation scheme is proposed to not only lower the voltages and power, but also remove the voltage matching constrains between resistive memory (RRAM) and selector. This makes threshold selector suitable for most of RRAM integration. View full abstract»

• Reduction of the Cell-to-Cell Variability in Hf1-xAlxOy Based RRAM Arrays by Using Program Algorithms

Publication Year: 2017, Page(s):175 - 178
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In this letter, we propose an effective route to reduce the cell-to-cell variability in 1T-1R-based random access memories (RRAM) arrays by combining the excellent switching performance of Hf1-xAlxOy with an optimized incremental step pulse with verify algorithm for programming. The strongly reduced cell-to-cell variability improves the thermal and post-programming... View full abstract»

• Functionally Complete Boolean Logic in 1T1R Resistive Random Access Memory

Publication Year: 2017, Page(s):179 - 182
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Nonvolatile stateful logic through RRAM is a promising route to build in-memory computing architecture. In this letter, a logic methodology based on 1T1R structure has been proposed to implement functionally complete Boolean logics. Arbitrary logic functions could be realized in two steps: initialization and writing. An additional read step is required to read out the logic result, which is in sit... View full abstract»

• A Surface-Potential-Based DC Model of Amorphous Oxide Semiconductor TFTs Including Degeneration

Publication Year: 2017, Page(s):183 - 186
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In this letter, for both non-degenerate conduction and degenerate conduction, a new compact model of amorphous oxide semiconductor thin-film transistors is developed. The contributions of the trapped and free charges are considered in the closed-form solutions of surface potential and drain current under a degenerate regime. Furthermore, proof of the model's accuracy has been obtained by compariso... View full abstract»

• Highly Enhanced Performance of Network Channel Polysilicon Thin-Film Transistors

Publication Year: 2017, Page(s):187 - 190
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This letter presents the electrical characteristics of newly proposed network-channel low-temperature polysilicon channel (LTPS) thin-film transistors (TFTs). Due to effective reduction of grain boundary traps and enhanced gate controllability, the network-channel TFTs show better subthreshold slope, lower threshold voltage, and higher ON- OFF current ratio, compared with conventional planar devic... View full abstract»

• Long-Term Depression Mimicked in an IGZO-Based Synaptic Transistor

Publication Year: 2017, Page(s):191 - 194
Cited by:  Papers (1)
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Amorphous indium-gallium-zinc oxide-based synaptic transistors with hafnium oxide (HfOx) insulating layer were fabricated to mimic synaptic long-term depression (LTD) characteristics. The fabrication temperature was less than 120°. Interval time of presynaptic spikes-dependent synaptic depression was first demonstrated in these IGZO-based synaptic transistors, which is important for computa... View full abstract»

• A Small-Area and Low-Power Scan Driver Using a Coplanar a-IGZO Thin-Film Transistor With a Dual-Gate for Liquid Crystal Displays

Publication Year: 2017, Page(s):195 - 198
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This letter proposes a small-area and low-power scan driver using a coplanar amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) with a dual gate for TFT liquid crystal displays. The size of the pull-up TFT of the proposed scan driver is reduced by 30% when the ON-current of the coplanar a-IGZO TFT with a dual gate increases by 65%, when compared with the coplanar a-IGZO TFT wi... View full abstract»

• Band-Bending Effect in the Characterization of Subgap Density-of-States in Amorphous TFTs Through Fully Electrical Techniques

Publication Year: 2017, Page(s):199 - 202
Cited by:  Papers (1)
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We report a model for the band-bending effect (BBE) for improved extraction of the subgap density-of-states (DOS) in amorphous semiconductor thin-film transistors (TFTs). In previous works, the potential (ψ(x)) across the amorphous active layer was assumed to be the same as the surface potential (ψS) over the active layer without the BBE. Due to the distributed DOS (g(E)) over the ba... View full abstract»

• Influence of Fast Charging on Accuracy of Mobility in ${a}$ -InHfZnO Thin-Film Transistor

Publication Year: 2017, Page(s):203 - 206
Cited by:  Papers (2)
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Amorphous InHfZnO (a-IHZO) thin-film devices have attracted considerable attention owing to their high mobility. However, the mobility of a-IHZO thin-film transistors has not been correctly determined, because it is affected by fast charging. In this letter, we investigated the effect of transient charging on the mobility. On the basis of the pulse IDS-VGS method, we present an approach to estimat... View full abstract»

• High-Performance Ti-Doped Zinc Oxide TFTs With Double-Layer Gate Dielectric Fabricated at Low Temperature

Publication Year: 2017, Page(s):207 - 209
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In this study, titanium (Ti)-doped zinc oxide thin film transistors (TiZO TFTs) with a double-layer gate dielectric were successfully fabricated on glass at low temperature. A stacked 7 nm-thick Al2O3/180 nm-thick SiO2 dielectric layer was used to improve the electrical performance of the TFTs, especially their leakage characteristics. Compared with the SiO2 View full abstract»

• Performance Enhancements in p-Type Al-Doped Tin-Oxide Thin Film Transistors by Using Fluorine Plasma Treatment

Publication Year: 2017, Page(s):210 - 212
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This letter reports on a tin oxide (SnO) thin-film transistor (TFT) with p-type conduction that uses aluminum (Al) doping in the SnO active channel layer. Performance enhancements were further achieved by applying fluorine plasma treatment on the p-type Al-doped SnO channel layer. The effects of the fluorine plasma treatment were also investigated.By tuning the power of the fluorine plasma treatme... View full abstract»

• Nb Doped TiO2 Protected Back-Channel-Etched Amorphous InGaZnO Thin Film Transistors

Publication Year: 2017, Page(s):213 - 216
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A new back-channel-etched process for the fabrication of amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) is demonstrated, in which a conductive Nb doped TiO2 (TNO) thin film is used to serve as protective layer for the a-IGZO active layer. It is shown that the TNO film provides the active layer with excellent protection even when the thickness is only 1 nm. With treatment by N View full abstract»

• Numerical Simulation for Operation of Flexible Thin-Film Transistors With Bending

Publication Year: 2017, Page(s):217 - 220
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We theoretically study the change of the performance characteristics with various mechanical bending conditions for flexible thin-film transistors (TFTs) by two-dimensional device simulation. The characteristics of newly developed flexible TFTs with high crystalline quality and high carrier mobility are more sensitive to the degree of bending. We developed a model to estimate the change in the cha... View full abstract»

• Realization of High Color Uniformity for Phosphor-Converted White Light-Emitting Diodes Through a Stamp-Printed Phosphor Coating

Publication Year: 2017, Page(s):221 - 224
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In this letter, we demonstrate a stamp-printed phosphor coating process to realize high angular color uniformity (ACU) for phosphor-converted white light-emitting diodes. In the proposed phosphor coating method, the phosphor gel is printed on desirable areas, where it forms variable geometries through the transfer of the stamp bump. The phosphor coating method shows high flexibility in its fabrica... View full abstract»

• Microcrystalline Silicon Photodiode For Large Area NIR Light Detection Applications

Publication Year: 2017, Page(s):225 - 227
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This letter reports on microcrystalline silicon near infrared (NIR) photodiode detector. The fabricated device shows dynamic ratio of 200 at 850 nm wavelength per 0.2 mW/cm2 of incident power density at reverse bias voltage of -1 V with response time of 400 μs. The dynamic ratio achieved here is 15 times higher than the state of art large area inorganic a-SiGe:H phototransistor a... View full abstract»

• New Distortion Correction Algorithm for Two-Dimensional Tetra-Lateral Position-Sensitive Silicon Photomultiplier

Publication Year: 2017, Page(s):228 - 231
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We present a 2-D tetra-lateral positionsensitive silicon photomultiplier (SiPM), featuring epitaxial quenching resistors and an intrinsic continuous cap resistive layer for charge division in this letter. The device has attractive advantages of less output electrodes and simple readout electronics, high position resolution, discrimination of photon number, high peak photon detection efficiency (PD... View full abstract»

• A Study of Vertical Thin Poly-Si Channel Transfer Gate Structured CMOS Image Sensors

Publication Year: 2017, Page(s):232 - 235
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In this letter, the image characteristics of CMOS image sensor (CIS) pixels using a vertical thin poly-Si channel (VTPC) transfer gate (TG) are established for the first time. The study of three-dimensional (3D) structures in the image sensor field has been started by 3D Flash memories. By adopting the poly-Si channel fabrication concept of 3D NAND flash memories-appropriately modified to fit the ... View full abstract»

• AlGaN/GaN MIS-HEMTs of Very-Low ${V}_{\sf {{th}}}$ Hysteresis and Current Collapse With In-Situ Pre-Deposition Plasma Nitridation and LPCVD-Si3N4 Gate Insulator

Publication Year: 2017, Page(s):236 - 239
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In this letter, we report an in-situ predeposition plasma nitridation process, which is adopted to remove the GaN surface oxygen-related bonds and reduce surface dangling bonds by forming Ga-N bonds prior to the low-pressure chemical vapor deposition (LPCVD)Si3N4 deposition. It demonstrates that the Vth hysteresis and current collapse of the device were dramatically improved ... View full abstract»

• Characterization of Dynamic Self-Heating in GaN HEMTs Using Gate Resistance Measurement

Publication Year: 2017, Page(s):240 - 243
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This letter reports on a new method for the characterization of transistors transient self-heating based on gate end-to-end resistance measurement. An alternative power signal is injected to the device output (between drain and source) at constant gate-to-source voltage. The dependence of gate resistance with temperature is used to extract the thermal impedance of the device in frequency domain vi... View full abstract»

Aims & Scope

IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

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Editor-in-Chief

Tsu-Jae King Liu
tking@eecs.berkeley.edu