Notice

# IEEE Transactions on Electron Devices

## Filter Results

Displaying Results 1 - 25 of 50

Publication Year: 2017, Page(s):C1 - 338
| PDF (208 KB)
• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2017, Page(s): C2
| PDF (139 KB)
• ### Performance and Variations Induced by Single Interface Trap of Nanowire FETs at 7-nm Node

Publication Year: 2017, Page(s):339 - 345
| | PDF (2022 KB) | HTML

DC/AC performance and the variations due to single interface trap of the nanowire (NW) FETs were investigated in the 7-nm technology node using fully calibrated TCAD simulation. Shorter junction gradient and greater diameter reduced RC delay without short channel degradations. Spacer with smaller dielectric constants decreased parasitic and gate capacitances with a slight decrease of ON-state curr... View full abstract»

• ### Laser Spike Annealing for Shallow Junctions in Ge CMOS

Publication Year: 2017, Page(s):346 - 352
| | PDF (2476 KB) | HTML

An annealing method capable of forming highly activated shallow junctions in Ge CMOS is still lacking. For the first time, nonmelt submillisecond laser spike annealing (LSA) is demonstrated to achieve high activation level, excellent diffusion control, and resulting low contact resistivity for both n-type and p-type Ge junctions when using P and B as the dopants, respectively. The thermal stabilit... View full abstract»

• ### Monolithic Integration of InAs Quantum-Well n-MOSFETs and Ultrathin Body Ge p-MOSFETs on a Si Substrate

Publication Year: 2017, Page(s):353 - 360
| | PDF (3260 KB) | HTML

Integration of InxGa1-xAs n-MOSFETs and SiyGe1-y p-MOSFETs could be a key to realize future low-power and high-speed logic circuits. In this paper, monolithic integration of InAs n-MOSFETs and Ge p-MOSFETs on a Si substrate is reported. To address the challenge of integrating materials with large lattice mismatch (InAs and Ge on Si substrate), a sub-120-nm GaSb-on-... View full abstract»

• ### A Deterministic and Self-Consistent Solver for the Coupled Carrier-Phonon System in SiGe HBTs

Publication Year: 2017, Page(s):361 - 367
| | PDF (2695 KB) | HTML

A stationary deterministic solver based on a spherical harmonics expansion of the Boltzmann transport equations for electrons, holes, and phonons is presented to study self-heating in ultrascaled bipolar transistors. With the electrothermal device simulator, a state-of-the-art toward-terahertz SiGe heterojunction bipolar transistor is analyzed and the simulation results are verified against experi... View full abstract»

• ### 3-D Analytical Modeling of Dual-Material Triple-Gate Silicon-on-Nothing MOSFET

Publication Year: 2017, Page(s):368 - 375
| | PDF (2000 KB) | HTML

A 3-D analytical model of a new structure, namely, dual-material triple-gate silicon-on-nothing MOSFET is proposed in this paper. 3-D Poisson's equation with proper boundary conditions was solved to obtain the surface potential variation of the structure considering the popular parabolic potential approximation, and the threshold voltage and electric field were calculated for the model. The propos... View full abstract»

• ### Anomalous Transconductance in Long Channel Halo Implanted MOSFETs: Analysis and Modeling

Publication Year: 2017, Page(s):376 - 383
Cited by:  Papers (1)
| | PDF (1722 KB) | HTML

In this paper, we report anomalous behavior of transconductance (gm) in halo implanted MOSFET for linear and saturation regions across both gate and body biases. The gm characteristics undergo sharp change of slope in saturation which cannot be modeled by conventional compact models. The cause of such behavior is identified and explained using the TCAD simulations of source s... View full abstract»

• ### Successive Conformal Mapping Technique to Extract Inner Fringe Capacitance of Underlap DG-FinFET and Its Variations With Geometrical Parameters

Publication Year: 2017, Page(s):384 - 391
| | PDF (1699 KB) | HTML

We propose a new analytical model based on successive conformal mapping to compute the bias dependent inner fringe capacitance in nonplanar multigate MOSFET structure with doping modulated source/drain (S/D) and gate underlap for sub 20-nm node. The conventional analytical model of capacitance and resistance for planar MOSFET cannot be applied to the nonplanar multigate MOSFET. This model consider... View full abstract»

• ### A Precision SiGe Reference Circuit Utilizing Si and SiGe Bandgap Voltage Differences

Publication Year: 2017, Page(s):392 - 399
Cited by:  Papers (1)
| | PDF (1901 KB) | HTML

Silicon-germanium (SiGe) BiCMOS technology platform provides designers with a unique opportunity to have access to both Si-Si and SiGe-Si p-n junctions. By taking advantage of the coexistence of these two p-n junctions, this paper presents a new temperature compensation technique for SiGe reference circuits. The source of the appearance of curvature in the thermal characteristics of reference circ... View full abstract»

• ### Semi-analytical Model of Charge Domain Propagation and Its Device Application

Publication Year: 2017, Page(s):400 - 406
| | PDF (1152 KB) | HTML

A semi-analytical theory is presented to describe the growth and propagation of generalized charge carrier instabilities in materials exhibiting negative differential drift velocity. This theory is applied to study the operation of a GaAs-based device, and its interaction with a resonant circuit. Results indicate the significance of an unstable accumulation domain, and are compared with Monte Carl... View full abstract»

• ### A Comprehensive Study of Reverse Current Degradation Mechanisms in Au/Ni/n-GaN Schottky Diodes

Publication Year: 2017, Page(s):407 - 411
| | PDF (1215 KB) | HTML

In this paper, we perform a comprehensive study on the reverse current degradation mechanisms in Au/Ni/n-GaN Schottky diodes based on an in-depth understanding on the defect-related current transport mechanisms. Instead of traditional Poole-Frenkel (PF) emission model, an extended bulk-limited PF transport process, including the compensation effect, is adopted to explain the variation of the PF cu... View full abstract»

• ### Design and Analysis of Polarity Controlled Electrically Doped Tunnel FET With Bandgap Engineering for Analog/RF Applications

Publication Year: 2017, Page(s):412 - 418
| | PDF (2552 KB) | HTML

In this paper, we investigate a polarity controlled electrically doped tunnel FET (ED-TFET) based on the bandgap engineering for analog/RF applications. The proposed device exhibits a heavily doped n-type Si-channel with two distinctive gate: 1) control gate (CG) and 2) polarity gate (PG). First, the work function of 4.72 eV is considered for CG and PG to convert the layer beneath CG and PG of int... View full abstract»

• ### Stabilizing Schemes for the Minority Failure Bits in Ta2O5-Based ReRAM Macro

Publication Year: 2017, Page(s):419 - 426
| | PDF (3399 KB) | HTML

A low-power 2-Mb Resistance random access memory (ReRAM) macro is developed in a 90-nm CMOS platform with a 3-nm-thick TaOx/Ta2O5 switching layer of the active area of 0.01 μm2. Instability of the ON-state minority bits degrades the high-temperature retention lifetime. The oxygen vacancies in the filament are annihilated by oxygen ions, which have... View full abstract»

• ### $1\times$ - to $2\times$ -nm perpendicular MTJ Switching at Sub-3-ns Pulses Below $100~\mu$ A for High-Performance Embedded STT-MRAM for Sub-20-nm CMOS

Publication Year: 2017, Page(s):427 - 431
| | PDF (1155 KB) | HTML

Magnetization switching is confirmed for sub-3-ns pulses below 100 μA in perpendicular magnetic tunnel junctions (MTJs) down to 16 nm in diameter. The magnetoresistance ratio exceeded 150%, satisfying requirements for fast read conditions. Using sub-30-nm MTJs, write-error rates of up to an order of -6 (10-6) are demonstrated. Read and write current margins, which are important device desig... View full abstract»

• ### Direct/Indirect Junction Between Channel Inversion Layer and Doped Source/Drain Region on Metal-Induced Lateral Crystallization Polycrystalline Silicon Bottom Gate TFTs

Publication Year: 2017, Page(s):432 - 437
| | PDF (1666 KB) | HTML

Top gate-structured thin-film transistors (TFTs) have a channel inversion region that is directly connected to the doped source/drain area. This stands in contrast with normal bottom gate-structured TFTs that have a channel inversion region on the downward facing side of the silicon layer regardless of the crystallinity. In this experiment, we fabricate a bottom gate TFT with a direct contact junc... View full abstract»

• ### Mechanism and Origin of Hysteresis in Oxide Thin-Film Transistor and Its Application on 3-D Nonvolatile Memory

Publication Year: 2017, Page(s):438 - 446
| | PDF (2175 KB) | HTML

Hysteresis in the current-voltage characteristics of a ZnO thin-film transistor (TFT) has been studied. Electric dipoles at the interface of the dielectric and the channel have been proposed as the agents responsible for the hysteresis. From experimental results and theoretical analysis, the water diffusing into the active layer is found as the main origin of the hysteresis. Based on this finding,... View full abstract»

• ### Corrosion Behavior and Metallization of Cu-Based Electrodes Using MoNi Alloy and Multilayer Structure for Back-Channel-Etched Oxide Thin-Film Transistor Circuit Integration

Publication Year: 2017, Page(s):447 - 454
Cited by:  Papers (1)
| | PDF (1424 KB) | HTML

Mo/Cu bilayer is the most conventional metal electrode with an excellent electrical conductivity and high environmental resistance for large-area back-channel-etch amorphous oxide thin-film transistors (TFTs) circuit integration. However, the Mo/Cu bilayer is metallized with a poor etch profile in conventional weak acidic H2O2-based etchant solution. This is attributed to the... View full abstract»

• ### Pinned Photodiode CMOS Image Sensor TCAD Simulation: In-Depth Analysis of in-Pixel Pinning Voltage Measurement for a Diagnostic Tool

Publication Year: 2017, Page(s):455 - 462
| | PDF (1600 KB) | HTML

TCAD simulations are conducted on a pinned photodiode (PPD), with the aim to reproduce the pinning voltage measurement developed by Tan et al. A thermionic model is proposed and detailed in order to explain the exponential injection occurring at an injection voltage higher than the pinning voltage, and the correct method to extract the transfer gate inversion voltage is given. Then, various nonide... View full abstract»

• ### Phosphor Temperature Overestimation in High-Power Light-Emitting Diode by Thermocouple

Publication Year: 2017, Page(s):463 - 466
| | PDF (855 KB) | HTML

Phosphor temperature in high-power white light-emitting diodes can greatly affect the optical properties, reliability, and lifetime. Accurate estimation of phosphor temperature is the first step for enhancing thermal management inside the package. In this paper, the phosphor temperature was measured by a plug-in method with thermocouple. The thermocouple's bead was inserted into the phosphor layer... View full abstract»

• ### Enhanced Optical and Thermal Performance of Eutectic Flip-Chip Ultraviolet Light-Emitting Diodes via AlN-Doped-Silicone Encapsulant

Publication Year: 2017, Page(s):467 - 471
| | PDF (2027 KB) | HTML

This paper investigated the optical and thermal performance of the nitride-based ultraviolet light-emitting diodes fabricated by the eutectic flip-chip method. A new packaging structure was proposed by introducing a thin encapsulation layer doped with 0.4 wt% AlN nanoparticles (NPs) and uniform quartz lens simultaneously. Experimental results showed that the packaging structure proposed in this pa... View full abstract»

• ### Achieving High-Performance Blue GaN-Based Light-Emitting Diodes by Energy Band Modification on AlxInyGa1–x–yN Electron Blocking Layer

Publication Year: 2017, Page(s):472 - 480
| | PDF (2230 KB) | HTML

We have achieved high-performance blue GaN-based light-emitting diodes (LEDs) by energy band modification on an AlxInyGa1-x-yN electron blocking layer (EBL). It is demonstrated by simulation that the strategy using high In/Al ratio to decrease polarization charge density and to alleviate the negative effect from polarization electric fields is more favorable. Using the optimal In/Al ratio of 0.5, ... View full abstract»

• ### Drain Extended Tunnel FET—A Novel Power Transistor for RF and Switching Applications

Publication Year: 2017, Page(s):481 - 487
| | PDF (2203 KB) | HTML

For the first time, a novel drain-extended tunnel FET (DeTFET) device is disclosed in this paper, while addressing the need for high-voltage/high-power devices for system-on-chip and automotive applications in beyond FinFET technology nodes. Operation of the proposed DeTFET device is presented with physics of band-to-band tunneling and associated carrier injection. Device's intrinsic (dc/switching... View full abstract»

• ### 4H-SiC Trench IGBT With Back-Side n-p-n Collector for Low Turn-OFF Loss

Publication Year: 2017, Page(s):488 - 493
| | PDF (1594 KB)

In this paper, an n-p-n collector incorporated in the back side of a 4H-SiC trench IGBT is presented to reduce the turn-off energy loss. A comparative study between the proposed structure and the conventional structure is conducted through ATLAS. The simulation results have demonstrated that the turn-off energy loss is reduced by more than 82.96% with a slight degradation in the on-state voltage d... View full abstract»

• ### The Influence of Processing Conditions on the 3-D Interconnected Structure of Nanosilver Paste

Publication Year: 2017, Page(s):494 - 499
| | PDF (816 KB) | HTML

Nanosilver paste is a promising material for power device interconnects. Interconnects are fabricated from nanosilver paste through a sintering process that drives off solvents and dispersants and fuses the silver particles. The integrity of the resulting interconnect is affected by the silver microstructure. This paper explored how sintering temperature, atmosphere, and time influenced microstruc... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy