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IEEE Design & Test

Issue 1 • Feb. 2017

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Displaying Results 1 - 25 of 29
  • [Front cover]

    Publication Year: 2017, Page(s): C1
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  • [Front inside cover]

    Publication Year: 2017, Page(s): C2
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  • IEEE Design&Test publication information

    Publication Year: 2017, Page(s): 1
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  • Table of contents

    Publication Year: 2017, Page(s):2 - 3
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  • 3D Test

    Publication Year: 2017, Page(s):4 - 5
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  • Guest Editors’ Introduction: Design & Test of a High-Volume 3-D Stacked Graphics Processor With High-Bandwidth Memory

    Publication Year: 2017, Page(s):6 - 7
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  • Unleashing Fury: A New Paradigm for 3-D Design and Test

    Publication Year: 2017, Page(s):8 - 15
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (739 KB) | HTML iconHTML

    This paper, based on an excellent keynote address by AMD's Jeff Rearick at 3D-TEST 2015, describes the design and test development of one of the world's first high-volume 3-D die stacks and hence a landmark product: AMD's Fury GPU. View full abstract»

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  • High-Bandwidth Memory (HBM) Test Challenges and Solutions

    Publication Year: 2017, Page(s):16 - 25
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1635 KB) | HTML iconHTML

    TSV-based 3-D stacking enables large-capacity, power-efficient DRAMs with high bandwidth, such as specified by JEDEC's HBM standard. This article is a written version of Jun's very interesting presentation at 3D-TEST 2015 on how such DRAM stacks are tested at SK hynix. View full abstract»

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  • High-Performance HBM Known-Good-Stack Testing

    Publication Year: 2017, Page(s):26 - 34
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2906 KB) | HTML iconHTML

    Based on Loranger's talk at 3D-TEST 2015, this article details the dedicated developments performed at probe-card supplier FormFactor and test-equipment supplier Teradyne to support the test of HBM DRAM stacks. View full abstract»

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  • Estimating the Impact of Methodology on Analog Integrated Circuit Design Time

    Publication Year: 2017, Page(s):35 - 46
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2049 KB) | HTML iconHTML

    The article discusses analog design practices and proposes a project management model for studying which analog design methodology will achieve the fastest time-to-market given the probability of design errors. View full abstract»

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  • Soft Error Mitigation Using Transmission Gate With Varying Gate and Body Bias

    Publication Year: 2017, Page(s):47 - 56
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (988 KB) | HTML iconHTML

    Soft errors not only are major threats to SRAM, but also have become a major threat to the reliability of logic circuits. This article proposes a new transmission-gate approach to filter out soft errors, and it is more efficient when to the thanks to its to compared state of art solutions, capability adjust gate and body bias voltages. View full abstract»

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  • A Comprehensive Design-for-Test Infrastructure in the Context of Security-Critical Applications

    Publication Year: 2017, Page(s):57 - 64
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (563 KB) | HTML iconHTML

    Testability is a perennial concern that requires ever-improved solutions; however, potentially resultant security vulnerabilities need to be considered as well. This article provides a compact look at a body of DfT work from lead practitioners in the field. The DfT strategies address predicting and data Potential impacts DfT controlling test volume and reducing power. of to security are considered... View full abstract»

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  • Test Generation Methods for Utilization Improvement of Hardware-Accelerated Simulation Platforms

    Publication Year: 2017, Page(s):65 - 76
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (620 KB) | HTML iconHTML

    Hardware-accelerated simulation platforms can significantly reduce the validation time. This article presents an off-platform test generation method and it compares and contrasts it against the on-platform alternative for two state-of-the-art multicore processor designs. View full abstract»

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  • Exploring Exploration: A Tutorial Introduction to Embedded Systems Design Space Exploration

    Publication Year: 2017, Page(s):77 - 90
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (875 KB) | HTML iconHTML

    As embedded systems grow more complex and as new applications such as IoT require many design constraints, sophisticated design space exploration techniques are essential in order to find the best compromise between different design goals and their tradeoff. This tutorial gives a structured insight into the field of design space exploration for embedded systems. View full abstract»

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  • Developing Great Products for the Immersive Computing Era

    Publication Year: 2017, Page(s):91 - 94
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (73 KB) | HTML iconHTML

    We stand at the precipice of the next great inflection point, and with it comes tremendous potential to build a new category of impactful and great products. If you look back at the last 100 years, there were four other technological inflection points that dramatically changed the world. The first was the introduction of the radio. For the first time the masses had more immediate access to informa... View full abstract»

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  • An Interview With Semiconductor Pioneer and EDA Visionary Leader Wally Rhines

    Publication Year: 2017, Page(s):95 - 105
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  • Report of the 2016 Embedded Systems Week (ESWEEK)

    Publication Year: 2017, Page(s):106 - 107
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  • The 2016 DAC Art Show Grand Prize Winner: Coventor, Inc.

    Publication Year: 2017, Page(s): 108
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  • Proceedings of the IEEE

    Publication Year: 2017, Page(s): 109
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  • CALL FOR PAPERS IEEE TRANSACTIONS ON MULTI-SCALE COMPUTING SYSTEMS

    Publication Year: 2017, Page(s): 110
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  • IEEE Collbratec

    Publication Year: 2017, Page(s): 111
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  • IEEE Embedded Systems Letters Now in Emerging Sources Citation Index

    Publication Year: 2017, Page(s):112 - 113
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  • IEEE Open Access Publishing

    Publication Year: 2017, Page(s): 114
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  • Test Technology TC Newsletter

    Publication Year: 2017, Page(s):115 - 117
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  • myIEEE

    Publication Year: 2017, Page(s): 118
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Aims & Scope

IEEE Design & Test offers original works describing the models, methods and tools used to design and test microelectronic systems from devices and circuits to complete systems-on-chip and embedded software. The magazine focuses on current and near-future practice, and includes tutorials, how-to articles, and real-world case studies. The magazine seeks to bring to its readers not only important technology advances but also technology leaders, their perspectives through its columns, interviews and roundtable discussions. Topics include semiconductor IC design, semiconductor intellectual property blocks, design, verification and test technology, design for manufacturing and yield, embedded software and systems, low-power and energy efficient design, electronic design automation tools, practical technology, and standards.  

It was published as IEEE Design & Test of Computers between 1984 and 2012.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Joerg Henkel
Chair for Embedded Systems (CES)
Karlsruhe Institute of Technology (KIT)